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freescale semiconductor data sheet: advance information document number: mpc5121e rev. 1, 10/2008 ? freescale semiconductor, inc., 2008. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mpc5121e/mpc5123 tepbga 27 mm x 27 mm the mpc5121e/mpc5123 integrates a high performance e300 cpu core based on the power architecture technology with a rich set of peripheral functions focused on communications and systems integration. major features of the mpc5121e/mpc5123 are: ? e300 power architecture proce ssor core (enhanced version of the mpc603e core), operates up to 400 mhz ? power modes include doze, nap, sleep, deep sleep, and hibernate ? axe ? fully programmable, 200 mhz 32-bit risc core for real-time acceleration tasks, such as audio. ? mbx lite ? 2d/3d graphics engine with powervr vector processing (only in mpc5121e, not in mpc5123) ? diu ? display interface unit ? ddr1, ddr2, and low-power mobile ddr (lpddr) sdram memory controller ? usb 2.0 otg controller with integrated physical layer (phy) ? dma subsystem ? emb ? flexible multi-function external memory bus interface ? nfc ? nand flash controller ? 10/100base ethernet ? pci interface, version 2.3 ? pata ? parallel ata integrated development environment (ide) controller ? sata ? serial ata controller with integrated physical layer (phy) ? sdhc ? mmc/sd/sdio card host controller ? psc ? programmable serial controller ? s/pdif ? serial audio interface ? can ? controller area network ? bdlc ? j1850 interface ? viu ? video input, itu-656 complient figure 1 shows a simplified mpc5121e/mpc5123 block diagram. mpc5121e/mpc5123 data sheet preliminary
mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 2 table of contents 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 pinout listings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 electrical and thermal characteristics . . . . . . . . . . . . . . . . . .16 3.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . .16 3.1.1 absolute maximum ratings . . . . . . . . . . . . . . . .16 3.1.2 recommended operating conditions . . . . . . . .17 3.1.3 dc electrical specifications. . . . . . . . . . . . . . . .18 3.1.4 electrostatic discharge . . . . . . . . . . . . . . . . . . .20 3.1.5 power dissipation . . . . . . . . . . . . . . . . . . . . . . .22 3.1.6 thermal characteristics. . . . . . . . . . . . . . . . . . .23 3.2 oscillator and pll electrical ch aracteristics . . . . . . . .24 3.2.1 system oscillator electr ical characteristics . . .25 3.2.2 rtc oscillator electrical characteristics . . . . . .25 3.2.3 system pll electrical characteristics. . . . . . . .25 3.2.4 e300 core pll electrical characteristics . . . . .26 3.3 ac electrical characteristics. . . . . . . . . . . . . . . . . . . . .27 3.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3.3.2 ac operating frequency data. . . . . . . . . . . . . .27 3.3.3 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.3.4 external interrupts . . . . . . . . . . . . . . . . . . . . . . .31 3.3.5 sdram (ddr) . . . . . . . . . . . . . . . . . . . . . . . . .31 3.3.6 pci. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 3.3.7 lpc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.3.8 nfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 3.3.9 pata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 3.3.10 sata phy . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.3.11 fec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.3.12 usb ulpi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.3.13 on-chip usb phy . . . . . . . . . . . . . . . . . . . . . . 59 3.3.14 sdhc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.3.15 diu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.3.16 spdif. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.17 can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.18 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.19 j1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.20 psc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.21 gpios and timers . . . . . . . . . . . . . . . . . . . . . . 72 3.3.22 fusebox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.3.23 ieee 1149.1 (jtag) . . . . . . . . . . . . . . . . . . . . . 73 3.3.24 viu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4 system design information . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.1 power up/down sequencing . . . . . . . . . . . . . . . . . . . . 75 4.2 system and cpu core avdd power supply filtering. 75 4.3 connection recommendations . . . . . . . . . . . . . . . . . . 76 4.4 pull-up/pull-down resistor requirements . . . . . . . . . 77 4.4.1 pull-down resistor requirements for test pin 77 4.4.2 pull-up requirements for the pci control lines77 4.5 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.1 trst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.5.2 e300 cop/bdm interface . . . . . . . . . . . . . . . . 78 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.2 mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . 82 6 product documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 preliminary
ordering information mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 3 figure 1. simplified mpc5121e/mpc5123 block diagram 1 ordering information table 1. mpc5121e orderable part numbers freescale part number speed (mhz) temperature (ambient) qualification package availability mpc5121vy400b 400 0 o c to 70 o c consumer rohs and pb-free tray mpc5121vy400br 400 0 o c to 70 o c consumer rohs and pb-free tape and reel mpc5121yvy400b 400 -40 o c to 85 o c industrial rohs and pb-free tray mpc5121yvy400br 400 -40 o c to 85 o c industrial rohs and pb-free tape and reel spc5121yvy400b 400 -40 o c to 85 o c automotive - aec rohs and pb-free tray spc5121yvy400br 400 -40 o c to 85 o c automotive - aec rohs and pb-free tape and reel table 2. mpc5123 orderable part numbers freescale part number speed (mhz) temperature (ambient) qualification package availability mpc5123vy300b 300 0 o c to 70 o c consumer rohs and pb-free tray mpc5123vy300br 300 0 o c to 70 o c consumer rohs and pb-free tape and reel mpc5123yvy300b 300 -40 o c to 85 o c industrial rohs and pb-free tray mpc5123yvy300br 300 -40 o c to 85 o c industrial rohs and pb-free tape and reel pmc ipic wdt gpt gpio i 2 c 3 can 4 j1850 sdhc spdif cfm psc 12 rtc 83 mhz (max) ip bus display ddr1/2 memory functionally multiplexed i/o lpc nfc pata emb 83 mhz ip bus axe engine 8 kb diu multi-port memory controller mbx lite graphics engine with vector processing fec usb2 + phy usb2 ulpi sata + phy pci 200 mhz ahb (32-bit) te m p f u s e 128 kb sram dma 64-channel e300 powerpc? 32-kb i-/32-kb d- cache 200 mhz csb bus (64-bit) reset/ jtag/cop clock i-cache viu not available in mpc5123 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 pin assignments freescale semiconductor 4 2 pin assignments this section details pin assignments. 2.1 pinout listings table 3 provides the pin-out listing for the mpc5121e/mpc5123. spc5123yvy300b 300 -40 o c to 85 o c automotive - aec rohs and pb-free tray SPC5123YVY300BR 300 -40 o c to 85 o c automotive - aec rohs and pb-free tape and reel mpc5123vy400b 400 0 o c to 70 o c consumer rohs and pb-free tray mpc5123vy400br 400 0 o c to 70 o c consumer rohs and pb-free tape and reel mpc5123yvy400b 400 -40 o c to 85 o c industrial rohs and pb-free tray mpc5123yvy400br 400 -40 o c to 85 o c industrial rohs and pb-free tape and reel spc5123yvy400b 400 -40 o c to 85 o c automotive - aec rohs and pb-free tray spc5123yvy400br 400 -40 o c to 85 o c automotive - aec rohs and pb-free tape and reel table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 1 of 12) signal package pin number pad type power supply notes ddr memory interface (67 total) mdq0 af5 ddr vdd_mem_io ? mdq1 ab6 ddr vdd_mem_io ? mdq2 ae4 ddr vdd_mem_io ? mdq3 af6 ddr vdd_mem_io ? mdq4 af7 ddr vdd_mem_io ? mdq5 ab8 ddr vdd_mem_io ? mdq6 ad6 ddr vdd_mem_io ? mdq7 ae6 ddr vdd_mem_io ? mdq8 ac7 ddr vdd_mem_io ? mdq9 af8 ddr vdd_mem_io ? mdq10 ab9 ddr vdd_mem_io ? mdq11 ad7 ddr vdd_mem_io ? mdq12 ae9 ddr vdd_mem_io ? mdq13 af10 ddr vdd_mem_io ? mdq14 ac9 ddr vdd_mem_io ? mdq15 af11 ddr vdd_mem_io ? table 2. mpc5123 orderable part numbers (continued) freescale part number speed (mhz) temperature (ambient) qualification package availability preliminary
pin assignments mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 5 mdq16 ad10 ddr vdd_mem_io ? mdq17 af12 ddr vdd_mem_io ? mdq18 ad11 ddr vdd_mem_io ? mdq19 ab12 ddr vdd_mem_io ? mdq20 ad12 ddr vdd_mem_io ? mdq21 ab13 ddr vdd_mem_io ? mdq22 af14 ddr vdd_mem_io ? mdq23 ad13 ddr vdd_mem_io ? mdq24 ae13 ddr vdd_mem_io ? mdq25 ac13 ddr vdd_mem_io ? mdq26 af15 ddr vdd_mem_io ? mdq27 ab14 ddr vdd_mem_io ? mdq28 ae16 ddr vdd_mem_io ? mdq29 ad15 ddr vdd_mem_io ? mdq30 ac15 ddr vdd_mem_io ? mdq31 ab15 ddr vdd_mem_io ? mdm0 ac6 ddr vdd_mem_io ? mdm1 ae8 ddr vdd_mem_io ? mdm2 af13 ddr vdd_mem_io ? mdm3 af16 ddr vdd_mem_io ? mdqs0 ad5 ddr vdd_mem_io ? mdqs1 ad8 ddr vdd_mem_io ? mdqs2 ac11 ddr vdd_mem_io ? mdqs3 ad14 ddr vdd_mem_io ? mba0 ad16 ddr vdd_mem_io ? mba1 ac16 ddr vdd_mem_io ? mba2 af19 ddr vdd_mem_io ? ma0 ad17 ddr vdd_mem_io ? ma1 ab16 ddr vdd_mem_io ? ma2 ae18 ddr vdd_mem_io ? ma3 af20 ddr vdd_mem_io ? ma4 ad18 ddr vdd_mem_io ? ma5 ab17 ddr vdd_mem_io ? ma6 ae19 ddr vdd_mem_io ? ma7 ac18 ddr vdd_mem_io ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 2 of 12) signal package pin number pad type power supply notes preliminary
mpc5121e/mpc5123 data sheet, rev. 1 pin assignments freescale semiconductor 6 ma8 af21 ddr vdd_mem_io ? ma9 ad19 ddr vdd_mem_io ? ma10 af22 ddr vdd_mem_io ? ma11 ac19 ddr vdd_mem_io ? ma12 ae21 ddr vdd_mem_io ? ma13 ad20 ddr vdd_mem_io ? ma14 ab19 ddr vdd_mem_io ? ma15 ae22 ddr vdd_mem_io ? mwe ad21 ddr vdd_mem_io ? mras af23 ddr vdd_mem_io ? mcas af24 ddr vdd_mem_io ? mcs ad22 ddr vdd_mem_io ? mcke ab20 ddr vdd_mem_io ? mck af17 ddr vdd_mem_io ? mck af18 ddr vdd_mem_io ? modt ac21 ddr vdd_mem_io ? lpc interface (8 total) lpc_clk aa4 general io vdd_io ? lpc_oe y5 general io vdd_io ? lpc_rw aa1 general io vdd_io ? lpc_cs0 w5 general io vdd_io ? lpc_cs1 y3 general io vdd_io ? lpc_cs2 y1 general io vdd_io ? lpc_ack aa2 general io vdd_io ? lpc_ax03 w4 general io vdd_io ? emb interface (35 total) emb_ax02 w3 general io vdd_io ? emb_ax01 v5 general io vdd_io ? emb_ax00 w2 general io vdd_io ? emb_ad31 w1 general io vdd_io ? emb_ad30 v4 general io vdd_io ? emb_ad29 u5 general io vdd_io ? emb_ad28 v3 general io vdd_io ? emb_ad27 v2 general io vdd_io ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 3 of 12) signal package pin number pad type power supply notes preliminary
pin assignments mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 7 emb_ad26 v1 general io vdd_io ? emb_ad25 u1 general io vdd_io ? emb_ad24 u3 general io vdd_io ? emb_ad23 t5 general io vdd_io ? emb_ad22 t1 general io vdd_io ? emb_ad21 t4 general io vdd_io ? emb_ad20 t3 general io vdd_io ? emb_ad19 r5 general io vdd_io ? emb_ad18 t2 general io vdd_io ? emb_ad17 r1 general io vdd_io ? emb_ad16 r3 general io vdd_io ? emb_ad15 p1 general io vdd_io ? emb_ad14 p2 general io vdd_io ? emb_ad13 p4 general io vdd_io ? emb_ad12 p5 general io vdd_io ? emb_ad11 p3 general io vdd_io ? emb_ad10 n1 general io vdd_io ? emb_ad09 n2 general io vdd_io ? emb_ad08 n3 general io vdd_io ? emb_ad07 n4 general io vdd_io ? emb_ad06 m1 general io vdd_io ? emb_ad05 m3 general io vdd_io ? emb_ad04 m5 general io vdd_io ? emb_ad03 l1 general io vdd_io ? emb_ad02 l2 general io vdd_io ? emb_ad01 l3 general io vdd_io ? emb_ad00 l4 general io vdd_io ? pata interface (9 total) pata _ c e 1 k1 general io vdd_io ata name: cs0 pata _ c e 2 l5 general io vdd_io ata name: cs1 pata_isolate k3 general io vdd_io ? pata _ i o r j1 general io vdd_io ata name: dior pata _ i ow k5 general io vdd_io ata name: diow pata_iochrdy j2 general io vdd_io ata name: iordy table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 4 of 12) signal package pin number pad type power supply notes preliminary
mpc5121e/mpc5123 data sheet, rev. 1 pin assignments freescale semiconductor 8 pata_intrq j3 general io vdd_io ? pata_drq j4 general io vdd_io ata name: dmarq pata _ dac k h2 general io vdd_io ata name: dmack nfc interface (7 total) nfc_wp g4 general io vdd_io ? nfc_rb h1 general io vdd_io ? nfc_we g3 general io vdd_io ? nfc_re g2 general io vdd_io ? nfc_ale h4 general io vdd_io ? nfc_cle h5 general io vdd_io ? nfc_ce0 h3 general io vdd_io ? i2c interface (6 total) i2c0_scl ac23 general io vdd_io ? i2c0_sda ad26 general io vdd_io ? i2c1_scl ab22 general io vdd_io ? i2c1_sda ab23 general io vdd_io ? i2c2_scl ac25 general io vdd_io ? i2c2_sda aa22 general io vdd_io ? irq interface (2 total) irq0 ac26 general io vdd_io ? irq1 ab25 general io vdd_io ? can interface (4 total) can1_rx c19 analog input vbat_rtc ? can1_tx a18 general io vdd_io ? can2_rx b19 analog input vbat_rtc ? can2_tx e16 general io vdd_io ? j1850 interface (2 total) j1850_tx y22 general io vdd_io ? j1850_rx aa24 general io vdd_io ? spdif interface (3 total) spdif_txclk ab21 general io vdd_io ? spdif_tx ad24 general io vdd_io ? spdif_rx ac24 general io vdd_io ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 5 of 12) signal package pin number pad type power supply notes preliminary
pin assignments mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 9 pci (54 total) pci_inta u23 pci vdd_io ? pci_rst_out f22 pci vdd_io ? pci_ad00 u24 pci vdd_io ? pci_ad01 v26 pci vdd_io ? pci_ad02 u25 pci vdd_io ? pci_ad03 r22 pci vdd_io ? pci_ad04 u26 pci vdd_io ? pci_ad05 t24 pci vdd_io ? pci_ad06 r23 pci vdd_io ? pci_ad07 t26 pci vdd_io ? pci_ad08 r26 pci vdd_io ? pci_ad09 p23 pci vdd_io ? pci_ad10 r24 pci vdd_io ? pci_ad11 r25 pci vdd_io ? pci_ad12 p26 pci vdd_io ? pci_ad13 p24 pci vdd_io ? pci_ad14 p25 pci vdd_io ? pci_ad15 n26 pci vdd_io ? pci_ad16 l22 pci vdd_io ? pci_ad17 k25 pci vdd_io ? pci_ad18 j26 pci vdd_io ? pci_ad19 k24 pci vdd_io ? pci_ad20 j25 pci vdd_io ? pci_ad21 h26 pci vdd_io ? pci_ad22 k23 pci vdd_io ? pci_ad23 j24 pci vdd_io ? pci_ad24 h24 pci vdd_io ? pci_ad25 j23 pci vdd_io ? pci_ad26 g25 pci vdd_io ? pci_ad27 j22 pci vdd_io ? pci_ad28 f26 pci vdd_io ? pci_ad29 g24 pci vdd_io ? pci_ad30 f24 pci vdd_io ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 6 of 12) signal package pin number pad type power supply notes preliminary
mpc5121e/mpc5123 data sheet, rev. 1 pin assignments freescale semiconductor 10 pci_ad31 h22 pci vdd_io ? pci_c/be 0 p22 pci vdd_io ? pci_c/be 1 n24 pci vdd_io ? pci_c/be 2 l24 pci vdd_io ? pci_c/be 3 g26 pci vdd_io ? pci_par n22 pci vdd_io ? pci_frame m23 pci vdd_io 4 pci_trdy m22 pci vdd_io 4 pci_irdy k26 pci vdd_io 4 pci_stop m24 pci vdd_io 4 pci_devsel l26 pci vdd_io 4 pci_idsel k22 pci vdd_io ? pci_serr m26 pci vdd_io 4 pci_perr m25 pci vdd_io 4 pci_req0 g23 pci vdd_io 4 pci_req1 e26 pci vdd_io 4 pci_req2 d26 pci vdd_io 4 pci_gnt0 e25 pci vdd_io ? pci_gnt1 g22 pci vdd_io ? pci_gnt2 e24 pci vdd_io ? pci_clk c26 pci vdd_io ? psc interface (61 total) psc_mclk_in c17 general io vdd_io ? psc0_0 d16 general io vdd_io ? psc0_1 a17 general io vdd_io ? psc0_2 e15 general io vdd_io ? psc0_3 c16 general io vdd_io ? psc0_4 b16 general io vdd_io ? psc1_0 c15 general io vdd_io ? psc1_1 a16 general io vdd_io ? psc1_2 e14 general io vdd_io ? psc1_3 a15 general io vdd_io ? psc1_4 d14 general io vdd_io ? psc2_0 c14 general io vdd_io ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 7 of 12) signal package pin number pad type power supply notes preliminary
pin assignments mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 11 psc2_1 b14 general io vdd_io ? psc2_2 e13 general io vdd_io ? psc2_3 a14 general io vdd_io ? psc2_4 d13 general io vdd_io ? psc3_0 af3 general io vdd_io ? psc3_1 ab5 general io vdd_io ? psc3_2 ac4 general io vdd_io ? psc3_3 ad4 general io vdd_io ? psc3_4 af4 general io vdd_io ? psc4_0 ab1 general io vdd_io ? psc4_1 aa3 general io vdd_io ? psc4_2 ab3 general io vdd_io ? psc4_3 aa5 general io vdd_io ? psc4_4 ac2 general io vdd_io ? psc5_0 ac1 general io vdd_io ? psc5_1 ac3 general io vdd_io ? psc5_2 ad1 general io vdd_io ? psc5_3 ad2 general io vdd_io ? psc5_4 ae3 general io vdd_io ? psc6_0 a11 general io vdd_io ? psc6_1 c10 general io vdd_io ? psc6_2 a10 general io vdd_io ? psc6_3 b9 general io vdd_io ? psc6_4 a9 general io vdd_io ? psc7_0 b8 general io vdd_io ? psc7_1 e10 general io vdd_io ? psc7_2 c8 general io vdd_io ? psc7_3 a8 general io vdd_io ? psc7_4 a7 general io vdd_io ? psc8_0 e9 general io vdd_io ? psc8_1 d8 general io vdd_io ? psc8_2 c7 general io vdd_io ? psc8_3 b6 general io vdd_io ? psc8_4 e8 general io vdd_io ? psc9_0 c6 general io vdd_io ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 8 of 12) signal package pin number pad type power supply notes preliminary
mpc5121e/mpc5123 data sheet, rev. 1 pin assignments freescale semiconductor 12 psc9_1 d7 general io vdd_io ? psc9_2 e7 general io vdd_io ? psc9_3 d6 general io vdd_io ? psc9_4 e6 general io vdd_io ? psc10_0 c13 general io vdd_io ? psc10_1 b13 general io vdd_io ? psc10_2 a13 general io vdd_io ? psc10_3 c12 general io vdd_io ? psc10_4 e12 general io vdd_io ? psc11_0 a12 general io vdd_io ? psc11_1 b11 general io vdd_io ? psc11_2 c11 general io vdd_io ? psc11_3 e11 general io vdd_io ? psc11_4 d11 general io vdd_io ? jtag (5 total) tck ab26 general io vdd_io 6 tdi y23 general io vdd_io 3 tdo w22 general io vdd_io ? tms y25 general io vdd_io 3 trst aa26 general io vdd_io 3 test / debug (2 total) test w25 general io vdd_io 2, 5 ckstp_out y26 general io vdd_io ? system control (3 total) hreset w24 general io vdd_io 1, 6 poreset w23 general io vdd_io 2, 6 sreset v22 general io vdd_io 1, 6 system clock (2 total) sys_xtali v24 analog input sys_pll_avdd oscillator input sys_xtalo w26 analog output sys_ pll_avdd oscillator output rtc (3 total) xtali_rtc c20 analog input vbat_rtc oscillator input xtalo_rtc a20 analog output vbat_rtc oscillator output hib_mode d18 analog output vbat_rtc ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 9 of 12) signal package pin number pad type power supply notes preliminary
pin assignments mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 13 gp input only (4 total) gpio28 a19 analog input vbat_rtc ? gpio29 e17 analog input vbat_rtc ? gpio30 c18 analog input vbat_rtc ? gpio31 b18 analog input vbat_rtc ? ddr reference voltage mvref ab11 analog input voltage reference for sstl input pads usb ? phy without power and ground supplies (7 total) usb_xtali c24 analog input usb_pll_pwr3 oscillator input usb_xtalo b24 analog output usb_ pll_pwr3 oscillator output usb_dp a23 analog io usb_vdda ? usb_dm a22 analog io usb_vdda ? usb_tpa a24 analog output ? ? usb_vbus d21 analog io ? ? usb_uid e19 analog input ? ? usb digital ios (2 total) usb2_vbus_pwr_fa ult b21 general io vdd_io ? usb2_drvvbus a21 general io vdd_io ? sata phy without power and ground supplies (7 total) sata_xtali c3 analog input sata_vdda_3p3 oscillator input sata_xtalo c2 analog output sata_vdda_3p3 oscillator output sata_anaviz e5 analog output ? sata phy debug output sata_txn e1 analog output sata_vdda_1p2 ? sata_txp f1 analog output sata_vdda_1p2 ? sata_rxp a5 analog input sata_vdda_1p2 ? sata_rxn a4 analog input sata_vdda_1p2 ? power and ground supplies (w ithout sata phy and usb phy) vdd_core k10, k11, k12, k13, k14, k15, k16, k17, l10, l17, m10, m17, n10, n17, p10, p17, r10, r17, t10, t17, u10, u11, u12, u13, u14, u15, u16, u17 power ? ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 10 of 12) signal package pin number pad type power supply notes preliminary
mpc5121e/mpc5123 data sheet, rev. 1 pin assignments freescale semiconductor 14 vdd_io b10, b15, b25, d10, d15, f11, f13, f14, f19, f23, f25, h21, j5, k2, k4, l23, l25, n6, n21, p6, p21, r2, r4, t23, t25, w6, w21, y2, y4, aa23, aa25, ae1, ae2, ae24, ae25, af2, af25 power ? ? vdd_mem_io aa8, aa13, aa14, ab18, ac5, ac10, ac14, ac20, ad9, ae5, ae10, ae15, ae20 power ? ? vss a2, a3, a25, b1,b2, b3, b5, b7, b12, b17, b20, b22, b26, c1, c4, c23, c25, d2, d12, d17, d24, d25, e18, f2, f3, f4, f5, f6, f8, f10, f16, f17, f21, g5, h6, h23, h25, k6, k21, l6, l11, l12, l13, l14, l15, l16, l21, m2, m4, m11, m12, m13, m14, m15, m16, n5, n11, n12, n13, n14, n15, n16, ground ? ? vss n23, n25, p11, p12, p13, p14, p15, p16, r11, r12, r13, r14, r15, r16, t6, t11, t12, t13, t14, t15, t16, t21, u2, u4, u6, u21, v23, v25, y24, aa6, aa10, aa11, aa16, aa17, aa21, ab2, ab4, ab10, ab24, ac8, ac12, ac17, ac22, ad3, ad25, ae7, ae12, ae17, ae23, ae26 ground ? ? sys_pll_avdd t22 analog power ? ? sys_pll_avss u22 analog ground ? ? core_pll_avdd aa19 analog power ? ? core_pll_avss ad23 analog ground ? ? vbat_rtc d19 power ? ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 11 of 12) signal package pin number pad type power supply notes preliminary
pin assignments mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 15 1) this pin is an input or open-drain output. this pin can not be configured. an external pull-up resistor is required. 2) this pin is an input only. this pin can not be configured. 3) these jtag pins have internal pull-up p-fets. this pin can not be configured. 4) this pins should have an external pull-up resistor. follow pci specification and see system design information. 5) this test pin must be tied to vss. 6) this pin contains an enabled internal schmitt-trigger. note this table indicates only the pins with permananently enabled internal pull-up, pull-down, or schmitt-trigger. most of the digital i/o pins can be configured to enable internal pull-up, pull-down, or schmitt-trigger. see mpc5121e reference manual, io control chapter. avdd_fusewr c9 power ? ? avdd_fuserd d9 power ? ? mvtt0 ab7 analog input sstl(ddr2) termination (odt) voltage mvtt1 af9 analog input sstl(ddr2) termination (odt) voltage mvtt2 ae11 analog input sstl(ddr2) termination (odt) voltage mvtt3 ae14 analog input sstl(ddr2) termination (odt) voltage power and ground supplies (usb phy) usb_pll_gnd e23 analog ground ? ? usb_pll_pwr3 d23 analog power ? ? usb_rref e22 analog power ? ? usb_vssa_bias b23 analog ground ? ? usb_vdda_bias d22 analog power ? ? usb_vssa c22, e20, e21 analog ground ? ? usb_vdda c21, d20 analog power ? ? power and ground supplies (sata phy) sata_resref e4 analog power ? ? sata_vdda_3p3 d4 analog power ? ? sata_vdda_1p2 c5, d1, e2 analog power ? ? sata_vdda_vreg d5 analog power ? ? sata_pll_vdda1p2 e3 analog power ? ? sata_pll_vssa d3 analog ground ? ? sata_rx_vssa a6, b4 analog ground ? ? sata_tx_vssa g1 analog ground ? ? table 3. mpc5121e/mpc5123 te-pbga pinout listing (sheet 12 of 12) signal package pin number pad type power supply notes preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 16 3 electrical and thermal characteristics 3.1 dc electrical characteristics 3.1.1 absolute maximum ratings the tables in this section describe the mp c5121e/mpc5123 dc electri cal characteristics. table 4 gives the absolute maximum ratings. table 4. absolute maximum ratings 1 1 absolute maximum ratings are stress ratings only, and fu nctional operation at the ma ximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage. characteristic sym min max unit specid supply voltage ? e300 core and peripheral logic vdd_core ? 0.3 1.47 v d1.1 supply voltage ? i/o buffers vdd_io, vdd_mem_io ? 0.3 3.6 v d1.2 supply voltage ? system apll, system oscillator sys_pll_avdd ? 0.3 3.6 v d1.3 supply voltage ? e300 apll core_pll_avdd ?0.3 3.6 v d1.4 supply voltage ? rtc (hibernation) vbat_rtc ? 0.3 3.6 v d1.5 supply voltage ? fuse programming avdd_fusewr ? 0.3 3.6 v d1.6 supply voltage ? fuse reading avdd_fuserd ? 0.3 3.6 v d1.7 supply voltage ? sata phy analog sata_vdda_3p3 ? 0.3 3.6 v d1.8 supply voltage ? sata phy voltage regulator sata_vdda_vreg ? 0.3 2.6 v d1.9 supply voltage ? sata phy tx/rx sata_vdda_1p2 ? 0.3 1.47 v d1.10 supply voltage ? sata phy pll sata_pll_vdda1p2 ? 0.3 1.47 v d1.11 supply voltage ? usb phy pll and osc usb_pll_pwr3 ? 0.3 3.6 v d1.12 supply voltage ? usb phy transceiver usb_vdda ? 0.3 3.6 v d1.13 supply voltage ? usb phy bandgap bias usb_vdda_bias ? 0.3 3.6 v d1.14 input voltage ? usb phy cable usb_vbus ? 0.3 3.6 v d1.15 input voltage (vdd_io) vin ? 0.3 vdd_io + 0.3 v d1.16 input voltage (vdd_mem_io) vin ? 0.3 vdd_mem_io + 0.3 v d1.17 input voltage (vbat_rtc) vin ? 0.3 vbat_rtc + 0.3 v d1.18 input voltage overshoot vinos ? 1 v d1.19 input voltage undershoot vinus ? 1 v d1.20 storage temperature range tstg ? 55 150 o c d1.21 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 17 3.1.2 recommended operating conditions table 5 gives the recommended operating conditions. 3) table 5. recommended operating conditions characteristic sym min 1 typ max 1 unit specid supply voltage ? e300 core and peripheral logic vdd_core 1.33 1.4 1.47 v d2.1 state retention voltage ? e300 core and peripheral logic 2 1.08 ?? vd2.2 supply voltage ? standard i/o buffers vdd_io 3.0 3.3 3.6 v d2.3 supply voltage ? memory i/o buffers (ddr) vdd_mem_io ddr 2.3 2.5 2.7 v d2.4 supply voltage ? memory i/o buffers (ddr2, lpddr) vdd_mem_io ddr2 vdd_mem_io lpddr 1.7 1.8 1.9 v d2.5 input reference voltage (ddr/ddr2) mvref 0.49*vdd_m em_io 0.50*vdd_m em_io 0.51*vdd_ mem_io vd2.6 termination voltage (ddr2) mvtt mvref-0.04 mvref mvref+ 0.04 vd2.7 supply voltage ? system apll, system oscillator sys_pll_avdd 3.0 3.3 3.6 v d2.8 supply voltage ? e300 apll core_pll_avdd 3.0 3.3 3.6 v d2.9 supply voltage ? rtc (hiberna tion) vbat_rtc 3.0 3.3 3.6 v d2.10 supply voltage ? fuse programming avdd_fusewr 3.3 3.6 v d2.11 supply voltage ? fuse reading avdd_fuserd 3.0 3.3 3.6 v d2.12 supply voltage ? sata phy analog and osc sata_vdda_3p3 3.0 3.3 3.6 v d2.13 supply voltage ? sata phy voltage regulator sata_vdda_vreg 1.7 2.6 v d2.14 supply voltage ? sata phy tx/rx sata_vdda_1p2 1.14 1.2 1.47 v d2.15 supply voltage ? sata phy pll sata_pll_vdda1p2 1.33 1.4 1.47 v d2.16 supply voltage ? usb phy pll and osc usb_pll_pwr3 3.0 3.3 3.6 v d2.17 supply voltage ? usb phy transceiver usb_vdda 3.0 3.3 3.6 v d2.18 supply voltage ? usb phy bandgap bias usb_vdda_bias 3.0 3.3 3.6 v d2.19 input voltage ? usb phy cable usb_vbus 1.4 ? 3.6 v d2.20 input voltage ? standard i/o buffers vin 0 ? vdd_io v d2.21 input voltage ? memory i/o buffers (ddr) vin ddr 0 ? vdd_mem _io ddr v d2.22 input voltage ? memory i/o buffers (ddr2) vin ddr2 0 ? vdd_mem _io ddr2 v d2.23 input voltage ? memory i/o buffers (lpddr) vin lpddr 0 ? vdd_mem _io lpdr v d2.24 ambient operating temperature range ta -40 ? +85 o c d2.25 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 18 3.1.3 dc electrical specifications table 6 gives the dc electrical characteris tics for the mpc5121e/mpc5123 at recommended operating conditions. 1 these are recommended and tested operating conditions. proper device operation outside these conditions is not guaranteed. 2 the state retention voltage can be applied to vdd_core after the device is placed in deep-sleep mode. table 6. dc electrical specifications characteristic condition sym min max unit specid input high voltage input type = ttl vdd_io v ih 0.51*vdd_io ? v d3.1 input high voltage input type = ttl vdd_mem_io ddr v ih mvref+0.15 ? v d3.2 input high voltage input type = ttl vdd_mem_io ddr2 v ih mvref+0.125 ? v d3.3 input high voltage input type = ttl vdd_mem_io lpddr v ih 0.7*vdd_io_mem l pddr ?vd 3 . 4 input high voltage input type = pci vdd_io v ih 0.5*vdd_io ? v d3.5 input high voltage input type = schmitt vdd_io v ih 0.65*vdd_io ? v d3.6 input high voltage sys_xtali crystal mode 1 bypass mode 2 cv ih vxtal+0.4v (vdd_io/2)+0.4v ?vd3.7 input high voltage sata_xtali crystal mode bypass mode sv ih vxtal+0.4v (vdd_io/2)+0.4v ?vd3.8 input high voltage usb_xtali crystal mode bypass mode uv ih vxtal+0.4v (vdd_io/2)+0.4v ?vd3.9 input high voltage rtc_xtali crystal mode 3 bypass mode 4 rv ih (vbat_rtc/5)+0.5v (vbat_rtc/2)+0.4v ?vd3.10 input low voltage input type = ttl vdd_io v il ? 0.42*vdd_io v d3.11 input low voltage input type = ttl vdd_mem_io ddr v il ? mvref-0.15 v d3.12 input low voltage input type = ttl vdd_mem_io ddr2 v il ? mvref-0.125 v d3.13 input low voltage input type = ttl vdd_mem_io lpddr v il ? 0.3*vdd_io_mem l pddr v d3.14 input low voltage input type = pci vdd_io v il ? 0.3*vdd_io v d3.15 input low voltage input type = schmitt vdd_io v il ? 0.35*vdd_io v d3.16 input low voltage sys_xtali crystal mode bypass mode cv il ? vxtal-0.4v (vdd_io/2)-0.4v v d3.17 input low voltage sata_xtali crystal mode bypass mode sv il ? vxtal-0.4v (vdd_io/2)-0.4v v d3.18 input low voltage usb_xtali crystal mode bypass mode uv il ? vxtal-0.4v (vdd_io/2)-0.4v v d3.19 input low voltage rtc_xtali crystal mode bypass mode rv il ? (vbat_rtc/5)-0.5v (vbat_rtc/2)-0.4v v d3.20 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 19 input leakage current vin = 0 or vdd_io/vdd_mem_io ddr/2 (depending on input type) 5 i in ? 2.5 2.5 a d3.21 input leakage current sys_xt al_in vin = 0 or vdd_io i in ?2 0 a d3.22 input leakage current rtc_xtal_in vin = 0 or vdd_io i in ?1 . 0 a d3.23 input current, pullup resistor 6 pullup vdd_io vin = vil i inpu 25 150 a d3.24 input current, pulldown resistor 8 pulldown vdd_io vin = vih i inpd 25 150 a d3.25 output high voltage ioh is driver dependent 7 vdd_io v oh 0.8*vdd_io ? v d3.26 output high voltage ioh is driver dependent 7 vdd_mem_io ddr v ohddr 1.94 ? v d3.27 output high voltage ioh is driver dependent 7 vdd_mem_io ddr2 v ohddr2 vdd_mem_io-0.28 ? v d3.28 output high voltage ioh is driver dependent 7 vdd_mem_io lpddr v ohlpdd r vdd_mem_io-0.28 ? v d3.28 output low voltage iol is driver dependent 7 vdd_io v ol ? 0.2*vdd_io v d3.30 output low voltage iol is driver dependent 7 vdd_mem_io ddr v olddr ?0 . 3 6v d 3 . 3 1 output low voltage iol is driver dependent 7 vdd_mem_io ddr2 v olddr2 ?0 . 2 8v d 3 . 3 2 output low voltage iol is driver dependent 7 vdd_mem_io lpddr v ollpdd r ?0 . 2 8v d 3 . 3 3 differential cross point voltage (ddr mck/mck ) ? v oxmck 0.5*vdd_mem_io ? 0.125 0.5*vdd_mem_io +0.125 v d3.34 dc injection current per pin 8 ? i cs ? 1.0 1.0 ma d3.35 input capacitance (digital pins) ? c in ?7p f d 3 . 3 6 input capacitance (analog pins) ? c in ? 10 pf d3.37 on die termination (ddr2) ? r odt 120 180 d3.38 1 this parameter is meant for those who do not use quartz crystals or resonators, but can osc, in crystal mode. in that case, vextal - vxtal - 400mv criteria has to be met for oscillator?s comparator to produce output clock. 2 this parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass mode. in that case, drive only the extal pin not connecting anyt hing to other pin for the oscillator?s comparator to produce output clock. 3 this parameter is meant for those who do not use quartz crystals or resonators, but can osc, in crystal mode. in that case, drive one of the xtal_in or xtal_out pins not connecting anyt hing to other pin for the oscillator?s comparator to produce output clock. table 6. dc electrical specifications (continued) characteristic condition sym min max unit specid preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 20 1 notes: 1. general io ? rise and fall times at drive load 50pf. 2. pci ? rise and fall times at drive load 10pf. 3. ddr ? for lpddr/mobile-ddr, slew rate is meas ured between 20 % vdd_io_mem and 80 % vdd_io_mem 4. ddr ? for ddr, ddr2, rising signals, slew rate is measured between v dd_io_mem * 0.5 and vih ac . for falling signals, slew rate is measured between vdd_io_mem * 0.5 and vil ac . 5. ddr ? rise and fall times terminated at the destination with 50 ohm to mvtt (0.5*vdd_io_mem) with 4pf, representing the ddr input capacitance. 3.1.4 electrostatic discharge caution this device contains circuitry that protects against damage due to high-static voltage or electrical fields. however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. operational reliability is enhanced if unused inputs are ti ed to an appropriate l ogic voltage level (gnd or vdd). table 10 gives package thermal char acteristics for this device. 4 this parameter is meant for those who do not use quartz crystals or resonators, but signal generator clock to drive, in bypass mode. in that case, drive only the xtal_in pin not connecting an ything to other pin for the oscillator?s comparator to produce output clock. 5 leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. 6 pullup current is measured at vil and pulldown current is measured at vih. 7 see ta b l e 7 for the typical drive capability of a specific signal pin bas ed on the type of output driver associated with that pin as listed in ta b l e 3 . 8 all injection current is transferred to vdd_io/vdd_mem_io. an ex ternal load is required to dissipate this current to maintain the power supply within t he specified voltage range. total injection current for all digital input-only and all digital input/output pins must not exceed 10 ma. exceeding this limi t can cause disruption of normal operation. table 7. i/o pads - drive current, slew rate pad type supply voltage drive select/slew rate control rise time max (ns) fall time max (ns) current ioh (ma) current iol (ma) specid general io vdd_io = 3.3v configuration 3 (11) 1.4 1.6 35 35 d3.41 configuration 2 (10) 9.8 12 d3.42 configuration 1 (01) 19 24 d3.43 configuration 0 (00) 140 183 d3.44 ddr vdd_mem_io = 2.5v (ddr) configuration 3 (011) 2 2 16.2 16.2 d3.45 vdd_mem_io = 1.8v (lpddr) configuration 0 (000) 1 1 4.6 4.6 d3.46 configuration 1 (001) 8.1 8.1 d3.47 vdd_mem_io = 1.8v (ddr2) configuration 2 (010) 1 1 5.3 5.3 d3.48 configuration 6 (110) 13.4 13.4 d3.49 pci vdd_io = 3.3v configurat ion 1 (1) 1.4 1.4 11 17 d3.50 configuration 0 (0) 2 2 d3.51 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 21 table 8. esd and latch-up protection characteristics sym rating min max unit specid v hbm human body model (hbm) ? jedec jesd22-a114-b 2000 ? v d4.1 v mm machine model (mm) ? jedec jesd22-a115 200 ? v d4.2 v cdm charge device model (cdm) ? jedec jesd22-c101 500 ? v d4.3 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 22 3.1.5 power dissipation power dissipation of the mpc5121e/mpc5123 is caused by 4 diff erent components: th e dissipation of the internal or core digital logic (supplied by vdd_core), the dissipation of the analog circuitry (supplied by sys_pll_avdd and core_pll_avdd), the dissipation of the io logic (supplie d by vdd_mem_io and vdd_io) and the dissipation of the phys (supplied by own supplies). table 9 details typical measured co re and analog power dissipation figures for a range of operating modes. however, the dissipation due to the switching of the io pins can not be given in general, but must be calculat ed for each application case us ing the following formula: eqn. 1 where n is the number of output pins switching in a group m, c is the capacitance per pin, vdd_io is the io voltage swing, f is the switching frequency and pioint is the power consumed by the unloaded io stage. the total power consumption of the mpc5121e/mpc5123 processor must not exceed the value, wh ich would cause the maximum junction temperature to be exceeded. eqn. 2 table 9. power dissipation core power supply (vdd_core) specid mode high-performance unit e300 = 300 mhz, csb = 200 mhz operational 1, 1 typical core power is measured at vdd_core = 1.4 v, tj = 25 c. note the maximum power depends on the supply voltage, process corner, junction temperature, and the concrete application and clock configurations. the worst case power consumption could reach a maximum of 2000 mw. 800 mw d5.1 deep-sleep 1, 1m w d 5 . 2 hibernation 20 uw d5.3 pll/osc power supplies ( sys_pll_avdd, core_pll_avdd) typical 25 mw d5.4 unloaded i/o power supplies (vdd_io, vdd_mem_io) ty p i c a l 3 0 0 m w d 5 . 5 phy power supplies (usb_vdda, sata_vdda) ty p i c a l 2 0 0 m w d 5 . 6 p io p ioint n m + cvdd _io 2 f = p total p core p analog p io pphys +++ = preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 23 3.1.6 thermal characteristics 3.1.6.1 heat dissipation an estimation of the chip -junction temperature, t j , can be obtained from the following equation: t j =t a +(r ja p d ) eqn. 3 where: t a = ambient temperature for the package (oc) r ja = junction to ambient thermal resistance (oc/w) p d = power dissipation in package (w) the junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determin ed on a single layer board, and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which value is correct depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usuall y appropriate if the board has low power dissi pation and the components are well separated. historically, the thermal resistance has frequently been expres sed as the sum of a junction to case thermal resistance and a ca se to ambient thermal resistance: table 10. thermal resistance data rating board layers sym value unit specid junction to ambient natural convection 1,2 1 junction temperature is a function of die size, on- chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. single layer board (1s) r ja 30 c/w d6.1 junction to ambient natural convection 1,3 3 per jedec jesd51-6 with the board horizontal. four layer board (2s2p) r jma 22 c/w d6.2 junction to ambient (@200 ft/min) 1,3 single layer board (1s) r jma 24 c/w d6.3 junction to ambient (@200 ft/min) 1,3 four layer board (2s2p) r jma 19 c/w d6.4 junction to board 4 4 thermal resistance between the die and the pr inted circuit board per jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. ?r jb 14 c/w d6.5 junction to case 5 5 thermal resistance between the die and the case t op surface as measured by the cold plate method (mil spec-883 method 1012.1). ?r jc 8c/wd6.6 junction to package top 6 6 thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. wh en greek letters are not available, the thermal characterization parameter is written as psi-jt. natural convection jt 2c/wd6.7 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 24 r ja =r jc +r ca eqn. 4 where: r ja = junction to ambient thermal resistance (oc/w) r jc = junction to case thermal resistance (oc/w) r ca = case to ambient thermal resistance (oc/w) r jc is device related and cannot be influenced by the user. you co ntrol the thermal environment to change the case to ambient thermal resistance, r ca . for instance, you can change th e air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal di ssipation on the printed circuit board surrounding the device. th is description is most useful for cer amic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. for most pack ages, a better model is required. a more accurate thermal model can be constr ucted from the junction to board thermal resistance and the junction to case thermal resistance. the junction to case co vers the situation where a heat sink is used or where a substantial amount of heat is dissip ated from the top of the package. the junction to board thermal resistance describes the th ermal performance when most of the heat is conducted to the printed circuit board. this model can be used for hand estimations or for a computational fluid dynamics (cfd) thermal model. to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j =t t +( jt p d ) eqn. 5 where: t t = thermocouple temperature on top of package (oc) jt = thermal characterization parameter (oc/w) p d = power dissipation in package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned, so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement erro rs caused by cooling effects of the thermocouple wire. 3.2 oscillator and pll electrical characteristics the mpc5121e/mpc5123 system requires a system-level clock i nput sys_xtali. this clock input may be driven directly from an external oscillato r or with a crystal using the internal oscillator. there is a separate oscillator for the independent real-time clock (rtc) system. the mpc5121e/mpc5123 clock generation uses two phase locked loop (pll) blocks. ? the system pll (sys_pll) takes an ex ternal reference frequency and genera tes the internal system clock. the system clock frequency is determined by the external reference frequency and the settings of the sys_pll configuration. ? the e300 core pll (core_pll) generates a master clock for all of the cpu circuitry. th e e300 core clock frequency is determined by the system clock frequency a nd the settings of the core_pll configuration. the usb phy contains its own oscillator with the input usb_xtali and an embedded pll. the sata phy contains its own oscillator with the input sata_xtali and an embedded pll. preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 25 3.2.1 system oscillator electrical characteristics the system oscillator can work in oscillator mode or in bypass mode to support an external input clock as clock reference. figure 2. timing diagram?sys_xtal_in 3.2.2 rtc oscillator electrical characteristics 3.2.3 system pll electrical characteristics table 11. system oscillator electrical characteristics characteristic sym min typical max unit specid sys_xtal frequency f sys_xtal 15.6 33.3 35.0 mhz o1.1 table 12. sys_xtal_in timing sym description min max units specid t cycle sys_xtali cycle time. 1,2 1 the sys_xtali frequency and system pll settings must be chos en such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. see the mpc5121e/mpc5123 reference manual. 2 the min/max cycle times are calculated using 1/f sys_xtal (min/max) where the f sys_xtal (min/max) (15.6/35 mhz) are taken from table 11 . 64.1 28.57 ns o.1.2 t rise sys_xtali rise time. 3 3 rise time is measured from 20% of vdd to 80% of vdd. 1 4 ns o.1.3 t fall sys_xtali fall time. 4 4 fall time is measured from 20% of vdd to 80% of vdd. 1 4 ns o.1.4 t duty sys_xtali duty cycle (measured at v m ) 5 5 sys_xtali duty cycle is measured at v m . 40 60 % o.1.5 table 13. rtc oscillator electrical characteristics characteristic sym min typical max unit specid rtc_xtal frequency f rtc_xtal ? 32.768 ? khz o2.1 table 14. system pll specifications characteristic sym min typical max unit specid sys pll input clock frequency 1 f sys_xtal 16 33.3 67 mhz o3.1 sys pll input clock jitter 2 t jitter ? ? 10 ps o3.2 t fall t rise t cycle sys_xtal_i clk t duty t duty cv ih cv il v m v m v m preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 26 3.2.4 e300 core pll electrical characteristics the internal clocking of the e300 core is generated from and s ynchronized to the system clock by means of a voltage-controlled core pll. sys pll vco frequency 1 f vcosys 400 ? 800 mhz o3.3 sys pll vco output jitter (dj), peak to peak / cycle f vcojitterdj ? ? 40 ps o3.4 sys pll vco output jitter (rj), rms 1 sigma f vcojitterrj ? ? 12 ps o3.5 sys pll relock time - after power up 3 t lock1 ? ? 200 so3.6 sys pll relock time - when power was on 4 t lock2 ? ? 170 so3.7 1 the sys_xtal frequency and pll conf iguration bits must be chosen such that the resulting system frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. 2 this represents total input jitter - short term and long term combined. two different types of jitter can exist on the input to core_syscl k, systemic and true random jitter. true random jitter is rejected. systemic jitter is passed into and through the pll to the internal clock circuitry. 3 pll-relock time is the maximum amount of time required for the pll lock after a stable vdd and core_sysclk are reached during the power-on reset sequence. 4 pll-relock time is the maximum amount of time required for the pll lock after the pll has been disabled and subsequently re-enabled during sleep modes. table 15. e300 pll specifications characteristic sym min typical max unit specid e300 frequency 1 1 the frequency and e300 pll configuration bits must be chosen such that the resulting system frequencies, cpu (core) frequency, and e300 pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies in ta bl e 1 6 . f core 50 ? 400 mhz o4.1 e300 pll vco frequency 1 f vcocore 400 ? 800 mhz o4.3 e300 pll input clock frequency f csb_clk 50 ? 200 mhz o4.4 e300 pll input clock cycle time t csb_clk 5 ? 20 ns o4.5 e300 pll relock time 2 2 pll-relock time is the maximum amount of time required for the pll lock after a stable vdd and core_sysclk are reached during the power-on reset s equence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep modes. t lock ? ? 200 so4.6 table 14. system pll specifications characteristic sym min typical max unit specid preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 27 3.3 ac electrical characteristics 3.3.1 overview hyperlinks to the indicated timing specification sections are provided below. ac test timing conditions: unless otherwise noted, all test conditions are as follows: ? ta = -40 to 85 o c ? vdd_core = 1.33 to 1.47 v vdd_io = 3.0 to 3.6 v ? input conditions: all inputs: tr, tf <= 1 ns ? output loading: all outputs: 50 pf 3.3.2 ac operating frequency data table 16 provides the operating frequency information for the mpc5121e/mpc5123. ? ac operating frequency data ? sdhc ? resets ? diu ? external interrupts ? spdif ? sdram (ddr) ? can ?pci ?i 2 c ?lpc ?j1850 ?nfc ?psc ?pata ?gpios and timers ? sata phy ? fusebox ? fec ? ieee 1149.1 (jtag) ?usb ulpi ?viu ?on-chip usb phy ? table 16. clock frequencies min max units specid e300 processor core 200 400 mhz a1.1 sdram clock 28.6 200 mhz a1.2 csb bus clock 50.0 200 mhz a1.3 ip bus clock 8.3 83 mhz a1.4 pci clock 4.43 66 mhz a1.5 lpc clock 2.08 83 mhz a1.6 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 28 notes: 1. the sys_xtal_in frequency, sys pll, a nd core pll settings must be chosen so that the resulting e300 clk, csb_clk, mck, frequencies do not exceed their respective maximum or minimum operating frequencies. 2. the values are valid for the user-operation mode. there can be deviations for test modes. 3. the selection of the peripheral clock frequencies needs to take care about requirements for baud rates and minimum frequency limitation. 4.the ddr data rate is 2x the ddr memory bus frequency. see the mpc5121e reference manual for more information on the clock subsystem. 3.3.3 resets the mpc5121e/mpc5123 has three reset pins: ? poreset - power on reset ?hreset - hard reset ?sreset - software reset these signals are asynchronous i/o signals an d can be asserted at any time. the input side uses a schmitt trigger and requires the same input characteristics as other mpc5121e/mpc5123 inputs , as specified in the dc elect rical specifications section. as long as vdd is not stable the hreset output is not stable. the timing relationship can be seen below. nfc clock 2.08 83 mhz a1.7 diu clock 0.78 100 mhz a1.8 sdhc clock 0.78 66.6 mhz a1.9 mbx clock 6.25 100 mhz a1.10 table 17. reset rise / fall timing description min max unit specid poreset 1 fall time 1 make sure that the poreset does not carry any glitches. the mpc5121e/mpc5123 has no filter to prevent them from getting into the chip. ?1m sa 3 . 4 poreset rise time ? 1 ms a3.5 hreset 2,3 fall time 2 hreset and sreset must have a monotonous rise time. 3 the assertion of hreset becomes active at power on reset without any sys_xtal clock. ?1m sa 3 . 6 hreset rise time ? 1 ms a3.7 sreset fall time ? 1 ms a3.8 sreset rise time ? 1 ms a3.9 table 16. clock frequencies (continued) min max units specid preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 29 figure 3. power-up behavior figure 4. power-on reset behavior poreset sreset hreset rst_conf[31:0] addr[31:0] t hrval t srval t s_por_conf t exec t h_por_conf sys_xtali sys_xtali poreset sreset hreset rst_conf[31:0] addr[31:0] t hrval t srval t s_por_conf t exec t h_por_conf t porhold preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 30 figure 5. hreset behavior figure 6. sreset behavior table 18. reset timing symbol description value sys_xtali specid t porhold time poreset must be held low before a qualified reset occurs 4 cycles a3.10 t hrval time hreset is asserted after a qualified reset occurs 26810 cycles a3.11 t srval time sreset is asserted after assertion of hreset 32 cycles a3.12 t exec time between s reset assertion and first core in struction fetch 4 cycles a3.13 sys_xtali poreset sreset hreset rst_conf[31:0] addr[31:0] t srval t exec t hrval t hrhold t hr_sr_delay no new fetch of the rst_conf sys_xtali poreset sreset hreset rst_conf[31:0] addr[31:0] t exec t srmin t srhold no new fetch of the rst_conf preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 31 3.3.4 external interrupts the mpc5121e/mpc5123 provides three different kinds of external interrupts: ? irq interrupts ? gpio interrupts with simple interrupt capability (not available in power-down mode) ? wakeup interrupts ipic inputs must be valid for at least tpicwid to ensure proper operation in edge triggered mode. 3.3.5 sdram (ddr) the mpc5121e/mpc5123 memory controller supports three types of ddr devices: ? ddr-1 (sstl_2 class ii interface) ? ddr-2 (sstl_18 interface) ? lpddr/mobile-ddr (1.8v i/o supply voltage) jedec standards define the minimum set of requirements for complient memory devices: ? jedec standard, ddr2 sdram specification, jesd79-2c, may 2006 ? jedec standard, double data rate (ddr ) sdram specification, jesd79e, may 2005 ? jedec standard, low power double data rate (lpddr) sdram specification, jesd79-4, may 2006 the mpc5121e/mpc5123 supports the configuration of two output drive strengths for ddr2 and lpddr: ? full drive strength ? half drive strengh (intended for ligther loads or point-to-point environments) the mpc5121e/mpc5123 memory controller supports dynamic on-die termination in the host device and in the ddr2 memory device. this section includes ac specifications for all ddr sdram pins. the dc paramete rs are specified in the dc electrical characteristics. t s_por_conf reset configuration setup time before assertion of poreset 1 cycle a3.14 t h_por_conf reset configuration hold time after assertion of poreset 1 cycle a3.15 t hr_sr_delay time from falling edge of hreset to falling edge of sreset 4 cycles a3.16 t hrhold time hreset must be held low before a qual ified reset occurs 4 cycles a3.17 t srhold time sreset must be held low before a qu alified reset occurs 4 cycles a3.18 t srmin time sreset is asserted after it has been qualifie d 1 cycles a3.19 table 19. ipic input ac timing specifications 1 1 t is the ip bus clock cycle. t= 12 ns is the minimum value (for the maximum ip bus freqency of 83 mhz). description symbol min unit specid ipic inputs - minimum pulse witdh t picwid 2t ns a4.1 table 18. reset timing (continued) symbol description value sys_xtali specid preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 32 3.3.5.1 ddr and ddr2 sdram ac timing specifications notes: 1. measured with clock pin loaded with differential 100 ohm termination resistor. 2. measured with all outputs except the clock loaded with 50 ohm termination resistor to vdd_io_mem/2. 3. all transitions measured at mid-supply (vdd_io_mem/2) 4. in this window, the first rising edge of dqs should occur. fr om the start of the window to dq s rising edge, dqs should be lo w. 5. window position is given for t dqsen = 2.0 t ck . for other values of t dqsen , window position is shifted accordingly. figure 7 shows the ddr sdram write timing. table 20. ddr and ddr2 (ddr2-400) sdram timing specifications at recommended operating cond itions with vdd_mem_io of 5% parameter symbol min max unit notes specid clock cycle time, cl=x t ck 5000 ? ps a5.1 mck ac differential crosspoint voltage v ix-ac vdd_io_mem*0.5 - 0.1 vdd_io_mem * 0.5 + 0.1 v1a5.2 ck high pulse width t ch 0.47 0.53 t ck 1,3 a5.3 ck low pulse width t cl 0.47 0.53 t ck 1,3 a5.4 skew between mck and dqs transitions t dqss ? 0.25 0.25 t ck 2,3 a5.5 address and control output setup time relative to mck rising edge t os(base) t ck /2 - 750 ? ps 2,3 a5.6 address and control output hold time relative to mck rising edge t oh(base) t ck /2 - 750 ? ps 2,3 a5.7 dq and dm output setup time relative to dqs t ds1(base) t ck /4 - 500 ? ps 2,3 a5.8 dq and dm output hold time relative to dqs t dh1(base) t ck /4 - 500 ? ps 2,3 a5.9 dqs-dq skew for dqs and associated dq inputs t dqsq - t ck /4 - 600 t ck /4 - 600 ps 3 a5.10 dqs window start position related to cas read command t dqsen tbd tbd ps 1,2,3,4,5 a5.11 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 33 figure 7. ddr write timing figure and figure 9 shows the ddr sdram read timing figure 8. ddr read timing, dq vs dqs figure 9. ddr read timing, dqsen figure 10 provides the ac test load for the ddr bus. mck dqs(out) dq, dm(out) t dqss t ds t dh dqs(in) any dq(in) t dqsq t dqsq t dqsq read mck command dqs(in) t dqsen(min) t dqsen address t oh t os preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 34 figure 10. ddr ac test load 3.3.6 pci the pci interface on the mpc5121e/mpc5123 is designed to pc i version 2.3 and supports 33 and 66 mhz pci operations. see the pci local bus specification; the component section specifies the electrical and timing parameters for pci components with the intent that components connect directly together whethe r on the planar or an expansion board, without any external buffers or other glue logic. parameters apply at th e package pins, not at expa nsion board edge connectors. the pci_clk is used as output clock, the mpc5121e/mpc5123 is a pci host device only. figure 11 shows the clock waveform and required measurement points for 3.3 v signaling environments. table 22 summarizes the clock specifications. figure 11. pci clk waveform 2 table 21. pci clk specifications sym description 66 mhz 1 1 in general, all 66 mhz pci components must work with any clock frequency up to 66 mhz. clk requirements vary depending upon whether the clock frequency is above 33 mhz. 33 mhz units specid min 2 2 rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in figure 11 . max min max t cyc pci clk cycle time 1,3 3 the minimum clock period must not be violated for any si ngle clock cycle, i.e., accounting for all system jitter. 15 30 30 ? ns a6.1 t high pci clk high time 6 ? 11 ? ns a6.2 t low pci clk low time 6 ? 11 ? ns a6.3 ? pci clk slew rate 2 1.5 4 1 4 v/ns a6.4 output z 0 = 50 r l = 50 vdd_mem_io/2 t cyc pci clk t low t high 0.4vcc 0.4vcc, p-to-p 0.3vcc 0.5vcc 0.6vcc 0.2vcc (minimum) preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 35 for measurement and test conditions, see the pci local bus specification. 3.3.7 lpc the local plus bus is the external bus interface of the mpc5121e/mpc 5123. a maximum of eight configurable chip selects (cs) are provided. there are two main modes of operation: non-muxed and muxed. the refe rence clock is the lpc clk. the maximum bus frequency is 83 mhz. definition of acronyms and terms: ws = wait state dc = dead cycle hc = hold cycle ds = data size in bytes bbt = burst bytes per transfer al = address latch enable length alt = chip select/address latch timing t lpcck = lpc clock period table 22. pci timing parameters 1 1 see the timing measurement conditions in the pci loca l bus specification. it is important that all driven signal transitions drive to their voh or vol level within one tcyc. sym description 66 mhz 33 mhz units specid min 2 2 minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the pci local bus specification. max min max t val clk to signal valid delay ? bused signals 1,2,3 26211nsa6.5 t val (ptp) clk to signal valid delay ? point to point 1,2,3 26212nsa6.6 t on float to active delay 1 2?2?nsa6.7 t off active to float delay 1 14 28 ns a6.8 t su input setup time to clk ? bused signals 3,4 3?7?nsa6.9 t su (ptp) input setup time to clk ? point to point 3,4 3 req# and gnt# are point-to-point signals and have diff erent input setup times than do bused signals. gnt# and req# have a setup of 5 ns at 66 mhz. all other signals are bused. 5 ? 10,12 ? ns a6.10 t h input hold time from clk 4 4 see the timing measurement conditions in the pci local bus specification. 0?0?nsa6.11 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 36 table 23. lpc timing sym description min max units specid t od cs [x], addr, r/w , tsiz, data (wr), ts , oe valid after lpc clk (output delay related to lpc clk) 05 n s a 7 . 1 t 1 non-muxed non-burst cs [x] pulse width (2+ws)*t lpcck (2+ws)*t lpcck ns a7.2 t 2 addr, r/w , tsiz, data (wr) valid before cs [x] assertion t lpcck -t od t lpcck +t od ns a7.3 t 3 oe assertion after cs [x] assertion t lpcck -t od t lpcck +t od ns a7.4 t 4 addr, r/w , tsiz, data (wr) hold after cs [x] negation t lpcck -t od (hc+1)*t lpcck +t od ns a7.5 t 5 ts pulse width t lpcck t lpcck ns a7.6 t 6 data (rd) setup before lpc clk 4 - ns a7.7 t 7 data (rd) input hold 0 (dc+1)*t lpcck ns a7.8 t 8 non-muxed read burst cs [x] pulse width (2+ws+bbt*(8/ds))*t lpcck (2+ws+bbt*(8/ds))*t lpcck ns a7.9 t 9 burst ack pulse width (bbt*(8/ds))*t lpcck (bbt*(8/ds))*t lpcck ns a7.10 t 10 burst data (rd) input hold 0 - ns a7.11 t 11 read burst ack assertion after cs [x] assertion (2+ws)*t lpcck (2+ws)*t lpcck ns a7.12 t 12 non-muxed write burst cs [x] pulse width (2.5+ws+bbt*(8/ds)) *t lpcck (2.5+ws+bbt*(8/ds)) *t lpcck ns a7.13 t 13 write burst addr, r/w , tsiz, data (wr) hold after cs [x] negation 0.5*t lpcck -t od (hc+0.5)*t lpcck +t od ns a7.14 t 14 write burst ack assertion after cs [x] assertion (2.5+ws)*t lpcck -t od (2.5+ws)*t lpcck +t od ns a7.15 t 15 write burst data valid t lpcck -t od - ns a7.16 t 16 non-muxed mode: asynchronous write burst addr valid before write data valid 0.5*t lpcck -t od 0.5*t lpcck +t od ns a7.17 t 17 muxed mode: addr cycle al*2*t lpcck -t od al*2*t lpcck ns a7.18 t 18 muxed mode: ale cycle al*t lpcck al*t lpcck ns a7.19 t 19 non-muxed mode page burst: addr cycle t lpcck -t od t lpcck ns a7.20 t 20 non-muxed mode page burst: burst data (rd) input setup before next addr cycle t od + t 6 ? ns a7.21 t 21 non-muxed mode page burst: burst data (rd) input hold after next addr cycle 0 ? ns a7.22 t 22 muxed mode: non-burst cs [x] pulse width (alt*(al*2)+2+ws)*t lpcck (alt*(al*2)+2+ws)*t lpcck ns a7.23 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 37 3.3.7.1 non-muxed mode 3.3.7.1.1 non-muxed non-burst mode figure 12. timing diagram ? non-muxed non-burst mode note ack is asynchonous input signal and has no timing requirements. ack needs to be deasserted after cs [x] is deasserted. t 23 muxed mode: read burst cs [x] pulse width (alt*(al*2)+2+ws+bbt*(8/ ds))*t lpcck (alt*(al*2)+2+ws+bbt*(8/ ds))*t lpcck ns a7.24 t 24 muxed mode: write burst cs [x] pulse width (alt*(al*2)+2.5+ws+bbt*( 8/ds))*t lpcck (alt*(al*2)+2.5+ws+bbt*( 8/ds))*t lpcck ns a7.25 table 23. lpc timing (continued) sym description min max units specid addr data (rd) cs [x] r/w data (wr) oe t 6 t 7 ts tsiz[1:0] ack t 1 lpc clk t 4 t lpcck t 2 t 3 t 5 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 38 3.3.7.1.2 non-muxed synchronous read burst mode figure 13. timing diagram ? non-muxed synchronous read burst mode 3.3.7.1.3 non-muxed synchronous write burst mode figure 14. timing diagram ? non-muxed synchronous write burst addr data ( rd ) cs [x] r/w oe ts ack lpc_clk valid address t 5 t 2 t 3 t 8 t 9 t 4 t 6 t 10 t 7 t 11 addr cs [x] r/w ts ack lpc_clk valid address data ( wr) t 5 t 2 t 13 t 12 t 14 t 9 t 15 t 15 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 39 3.3.7.1.4 non-muxed asynchronous read burst mode (page mode) figure 15. timing diagram ? non- muxed asynchronous read burst 3.3.7.1.5 non-muxed aynchronous write burst mode figure 16. timing diagram ? non-muxed aynchronous write burst addr[31:n+1] data ( rd ) cs [x] r/w oe ts ack lpc_clk valid address (page address) addr[n:0] valid address valid address t 5 t 2 t 3 t 9 t 4 t 6 t 10 t 7 t 8 t 11 t 19 t 20 t 21 addr[31:n+1] cs [x] r/w ts ack lpc_clk valid address (page address) addr[n:0] valid address valid address data ( wr) t 5 t 2 t 13 t 12 t 14 t 9 t 15 t 15 t 16 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 40 3.3.7.2 muxed mode 3.3.7.2.1 muxed non-burst mode figure 17. timing diagram ? muxed non-burst mode note ack is asynchonous input signal and has no timing requirements. ack needs to be deasserted after cs [x] is deasserted. lpc_clk ad[31:0] (wr) cs [x] r/w ale address ts valid write data ad[31:0] (rd) oe address ack t 18 t 4 t 5 t 22 t 3 t 17 t 7 t 6 tsiz[1:0] preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 41 3.3.7.2.2 muxed synchr onous read burst mode figure 18. timing diagram ? muxed synchronous read burst 3.3.7.2.3 muxed synchr onous write burst mode figure 19. timing diagram ? muxed synchronous write burst lpc_clk csx r/w ale ack ts oe ad[31:0] (rd) address t 3 t 18 t 5 t 23 t 6 t 10 t 7 t 9 t 17 t 11 lpc_clk ad[31:0] (wr) csx r/w ale address ack ts t 9 t 5 t 24 t 18 t 17 t 15 t 15 t 14 t 13 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 42 3.3.8 nfc the nand flash controller (nfc) implements the interface to st andard nand flash memory devi ces. this section describes the timing parameters of the nfc. figure 20. command latch cycle timing figure 21. address latch cycle timing nfc_cle nfc_ce[1:0] nfc_we nfc_ale nfio[7:0] command tdh tds tcls tclh twp tcs tch tals talh nfc_cle nfc_ce[1:0] nfc_we nfc_ale nfio[7:0] address tdh tds tcls twp tcs tch tals twh twc talh preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 43 figure 22. write data latch timing figure 23. read data latch timing table 24. nfc timing characteristics timing parameter description min. value max. value unit specid tcls nfc_cle setup time t+1 ? ns a8.1 tclh nfc_cle hold time t-1 ? ns a8.2 tcs nfc_ce[1:0] setup time 2t-1 ? ns a8.3 tch nfc_ce[1:0] hold time t ? ns a8.4 nfc_cle nfc_ce[1:0] nfc_we nfc_ale nfio[15:0] data to nf tdh tds tcls twp tcs twh twc nfc_cle nfc_ce[1:0] nfc_re nfc_ale nfio[15:0] data from nf trp trea treh trc trhz trr tar r/b preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 44 t is the flash clock cycle. t= 45 ns, frequency = 22 mhz (boo t configuration, ip bus = 66 mhz) t= 36 ns, frequency = 27 mhz (maximum configurable frequency, ip bus = 83 mhz) 3.3.9 pata the mpc5121e/mpc5123 ata controller (pata) is completely software programmable. it can be programmed to operate with ata protocols using their respectiv e timing, as described in the ansi ata-4 specifica tion. the ata interface is completely asynchronous in nature. signal relationships are based on specific fixed timing in terms of timing units (nanoseconds). ata data setup and hold times, with respect to read/write str obes, are software programmable inside the ata controller. data setup and hold times are implemented using counters. the counters count the number of ata clock cycles needed to meet the ansi ata-4 timing specifications. for details , see the ansi ata-4 specification and how to program an ata controller and ata drive for different ata protocols and their respecti ve timing. see the mpc5121e/mpc5123 reference manual. the mpc5121e/mpc5123 ata host controller design makes data available coincidentally with the active edge of the write strobe in pio and multiword dma modes. ? write data is latched by the drive at the inactive edge of the write strobe. this gives ample setup-time beyond that required by the ata-4 specification. ? data is held unchanged until the next active edge of the write strobe. th is gives ample hold-time beyond that required by the ata-4 specification. all ata transfers are programmed in terms of system clock cycles (ip bus clocks) in the ata host controller timing registers. this puts constraints on the ata protocols and their respectiv e timing modes in which the at a controller can communicate with the drive. twp nfc_wp pulse width t-1 ? ns a8.5 tals nfc_ale setup time t-1 ? ns a8.6 talh nfc_ale hold time t-1 ? ns a8.7 tds data setup time t-2 ? ns a8.8 tdh data hold time t-1 ? ns a8.9 twc write cycle time 2t ? ns a8.10 twh nfc_we hold time t-1 ? ns a8.11 trr ready to nfc_re low 5t+2 ? ns a8.12 trp nfc_re pulse width 1.5t-1 ? ns a8.13 trc read cycle time 2t ? ns a8.14 treh nfc_re high hold time 0.5t ? ns a8.15 table 24. nfc timing characteristics (continued) timing parameter description min. value max. value unit specid preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 45 faster ata modes (i.e., udma 0, 1, 2) are supported when the sy stem is running at a sufficient frequency to provide adequate data transfer rates. adequate data tran sfer rates are a function of the following: ? the mpc5121e/mpc5123 operating frequency (ip bus clock frequency) ? internal mpc5121e/mpc5123 bus latencies ? other system load dependent variables the ata clock is the same frequency as the ip bus cloc k in mpc5121e/mpc5123. see the mpc5121e/mpc5123 reference manual. note all output timing numbers are specified for nominal 50 pf loads. 3.3.9.1 pata timing parameters in the timing equations , some timing parameters are used. these paramete rs depend on the implementation of the ata interface in silicon, the bus transceiver used, the cable delay and cable skew. the parameters shown in table 3-25 specify the ata timing. table 3-25. pata timing parameters name meaning controlled by value specid t pata bus clock period mpc5121e/m pc5123 15 ns a9.1 ti_ds set-up time ata_data to ata_iordy edge (udma-in only) mpc5121e/m pc5123 2 ns a9.2 ti_dh hold time ata_iordy edge to ata_data (udma-in only) mpc5121e/m pc5123 5 ns a9.3 tco propagation delay bus clock l-to-h to: ata_cs0, ata_cs1, ata_da2, ata _ da 1 , ata _ da 0 , ata _ d i o r , ata _ d i ow, ata _ d m ac k , ata _ data , ata _ b u f f e r _ e n mpc5121e/m pc5123 2 ns a9.4 tsu set-up time ata_data to bus clock l-to-h mpc5121e/m pc5123 2 ns a9.5 tsui set-up time ata_iordy to bus clock h-to-l mpc5121e/m pc5123 2 ns a9.6 thi hold time ata_iordy to bus clock h to l mpc5121e/m pc5123 2 ns a9.7 tskew1 max difference in propagation delay bus clock l-to-h to any of following s i g n a l s : ata _ c s 0 , ata _ c s 1 , ata _ da 2 , ata _ da 1 , ata _ da 0 , ata _ d i o r , ata _ d i ow, ata _ d m ac k , ata _ data ( w r i t e ) , ata _ b u f f e r _ e n mpc5121e/m pc5123 1.7 ns a9.8 tskew2 max difference in buffer propagation delay for any of following signals: ata _ c s 0 , ata _ c s 1 , ata _ da 2 , ata _ da 1 , ata _ da 0 , ata _ d i o r , ata _ d i ow, ata _ d m ac k , ata _ data ( w r i t e ) , ata _ b u f f e r _ e n transceiver a9.9 tskew3 max difference in buffer propagation delay for any of following signals: ata _ i o r dy, ata _ data ( r e a d ) transceiver a9.10 tbuf max buffer propagation delay transceiver a9.11 tcable1 cable propagation delay for ata_data cable a9.12 tcable2 cable propagation delay for control signals: ata_dior, ata_diow, ata _ i o r dy, ata _ d m ac k cable a9.13 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 46 3.3.9.2 pio mode timing a timing diagram for the pio read mode is given in figure 24 . figure 24. pio read mode timing to fulfill read mode timing, the different timing parameters given in table 3-26 must be observed. tskew4 max difference in cable propagation delay between: ata_iordy and ata_data (read) cable a9.14 tskew5 max difference in cable propagation delay between: ata_dior, ata _ d i ow, ata _ d m ac k a n d ata _ c s 0 , ata _ c s 1 , ata _ da 2 , ata _ da 1 , ata _ da 0 , ata _ data ( w r i t e ) cable a9.15 tskew6 max difference in cable propagation delay without accounting for ground bounce cable a9.16 table 3-26. timing parameters pio read ata parameter pio read mode timing parameter value how to meet specid t1 t1 t1(min) = time_1 * t - (tskew1 + tskew2 + tskew5) calculate and programming time_1, see reference manual a9.20 t2 t2r t2(min) = time_2r * t - (tskew1 + tskew2 + tskew5) calculate and programming time_2r, see reference manual a9.21 t9 t9 t9(min) = time_9 * t - (tskew1 + tskew2 + tskew6) calculate and programming time_9, see reference manual a9.22 table 3-25. pata timing parameters (continued) name meaning controlled by value specid addr dior read data (15:0) iordy iordy t1 t2r t9 t5 ta t6 trd1 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 47 in pio write mode, timing waveforms ar e somewhat different as shown in figure 25 . figure 25. pio write mode timing to fulfill this timing, several paramete rs need to be observed as shown in table 3-27 . t5 t5 t5(min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 if not met, increase time_2r a9.23 t6 t6 0 ? a9.24 ta ta ta(min) = (1.5 + time_ax) * t - (tco + tsui + tcable2 + tcable2 + 2*tbuf) calculate and programming time_ax, see reference manual a9.25 trd trd1 trd1(max) = (-trd) + (tskew3 + tskew4) trd1(min) = (time_pio_rdx - 0.5 )*t - (tsu + thi) (time_pio_rdx - 0.5) * t > tsu + thi + tskew3 + tskew4 calculate and programming time_pio_rdx, see reference manual a9.26 t0 ? t0(min) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9 a9.27 table 3-26. timing parameters pio read (continued) ata parameter pio read mode timing parameter value how to meet specid addr dior write data (15:0) iordy iordy t1 t2r t9 diow buffer_en ton ta tb t4 toff t1 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 48 table 3-27. timing parameters pio write ata parameter pio write mode timing parameter value how to meet specid t1 t1 t1(min) = time_1 * t ? (tskew1 + tskew2 + tskew5) time_1, see reference manual a9.30 t2 t2r t2(min) = time_2w * t - (tskew1 + ts kew2 + tskew5) calculate and programming time_2w, see reference manual a9.31 t9 t9 t9(min) = time_9 * t - (tskew1 + tskew2 + tskew6) time_9, see reference manual a9.32 t3 ? t3(min) = (time_2w - time_on)* t - (tskew1 + tskew2 +tskew5) if not met, increase time_2w a9.33 t4 t4 t4(min) = time_4 * t - tskew1 calculate and programming time_4, see reference manual a9.34 ta ta ta = (1.5 + time_ax) * t - (tco + tsui + tcable2 + tcable2 + 2*tbuf) calculate and programming time_ax, see reference manual a9.35 t0 ? t0(min) = (time_1 + time_2 + time_9) * t time_1, time_2r, time_9 a9.36 ? ? avoid bus contention when switching buffer on by making ton long enough ? a9.37 ? ? avoid bus contention when switching buffer off by making toff long enough ? a9.38 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 49 3.3.9.3 timing in multiword dma mode timing in multiword dma mode is given in figure 26 and figure 27. figure 26. mdma read timing figure 27. mdma write timing to meet this timing, a number of timing parameters must be controlled as shown in table 3-28 . dmarq addr dmack dior read data (15:0) tk1 tm td tk tgr tfr tkjn dmarq addr dmack diow write data (15:0) tk1 tm tdtk tkjn toff buffer_en ton td1 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 50 3.3.9.4 udma in timing diagrams udma mode timing is more complicated than pio mode or mdma mode. in this section, timing diagrams for udma in are given: ? figure 28 gives timing for udma in transfer start ? figure 29 gives timing for host terminating udma in transfer ? figure 30 gives timing for device terminating udma in transfer. table 3-28. timing parameters mdma read and write ata parameter mdma read/write timing parameter value how to meet specid tm, ti tm tm(min) = ti(min) = time_m * t ? (tskew1 + tskew2 + tskew5) calculate and programming time_m, see reference manual a9.40 td td, td1 td1(min) = td(min) = time_d * t ? (tskew1 + tskew2 + tskew6) calculate and programming time_d, see reference manual a9.41 tk tk tk(min) = time_k * t ? (tskew1 + tskew2 + tskew6) calculate and programming time_k, see reference manual a9.42 t0 ? t0(min) = (time_d + time_k) * t time_d, time_k a9.43 tg(read) tgr tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min-drive) = td ? te(drive) time_d, see reference manual a9.44 tf(read) tfr tfr(min-drive) =0 ? a9.45 tg(write) ? tg(min-write) = time_d * t ?( tskew1 + tskew2 + tskew5) time_d a9.46 tf(write) ? tf(min-write) = time_k * t ?(tskew1 + tskew2 + tskew6) time_k a9.47 tl ? tl(max) = (time_d + time_k-2)*t ? (tsu + tco + 2*tbuf + 2*tcable2) time_d, time_k a9.48 tn, tj tkjn tn= tj= tkjn = (max(time_k,. time_jn) * t ?(tskew1 + tskew2 + tskew6) calculate and programming time_jn, see reference manual a9.49 ?t o n toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ? a9.50 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 51 figure 28. udma in transfer start timing diagram tc1 tc1 tenv tds tdh tack addr dmarq dmack dior diow data read iordy preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 52 figure 29. udma in host terminates transfer figure 30. udma in device terminates transfer timing parameters are explained in table 29 . addr dmarq dmack dior diow iordy data read data write buffer_en tack trp tc1 tc1 tx1 tmli tds tdh tmli tzah tzah ton tdzfs tcvh toff tack tmli tc1 tc1 tss1 tli5 tmli tzah tzah ton tdzfs tcvh toff tds tdh addr dmarq dmack dior diow iordy data read data write buffer_en preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 53 3.3.9.5 udma out timing diagrams udma mode timing is more complicated than pio mode or mdma mode. in this section, timing diagrams for udma out are given: ? figure 31 gives timing for udma out transfer start ? figure 32 gives timing for host terminating udma out transfer ? figure 33 gives timing for device terminating udma out transfer. table 29. timing parameters udma in burst ata parameter udma in timing parameter value how to meet specid tack tack tack(min) = (time_ack * t) ? (tskew1 + tskew2 ) calculate and programming time_ack, see reference manual a9.51 tenv tenv tenv(min) = (time_env * t) ? (tskew1 + tskew2) tenv(max) = (time_env * t) + (tskew1 + tskew2) calculate and programming time_env, see reference manual a9.52 tds tds1 tds ? (tskew3) ? ti_ds > 0 tskew3, ti_ds, ti_dh should be low enough a9.53 tdh tdh1 tdh ? (tskew3) ?ti_dh > 0 a9.54 tcyc tc1 (tcyc ? tskew ) > t bus clock period t big enough a9.55 trp trp trp(min) = time_rp * t ? (tskew1 + tskew2 + tskew6) calculate and programming time_rp, see reference manual a9.56 ? tx1 1 1 there is a special timing requirement in the ata host that requi res the internal diow to go only high three clocks after the last active edge on the dstrobe signal. the equation gi ven on this line tries to capture this constraint. (time_rp * t) ? (tco + tsu + 3t + 2 *tbuf + 2*tcable2) > trfs (drive) calculate and programming time_rp, see reference manual a9.57 tmli tmli1 tmli1(min) = (time_mlix + 0.4) * t calculate and programming time_mlix, see reference manual a9.58 tzah tzah tzah(min) = (time_zah + 0.4) * t calculate and programming time_zah, see reference manual a9.59 tdzfs tdzfs tdzfs = (time_dzfs * t) ? (tskew1 + tskew2) calculate and programming time_dzfs, see reference manual a9.60 tcvh tcvh tcvh = (time_cvh *t) ? (tskew1 + tskew2) calculate and programming time_cvh, see reference manual a9.61 ? ton toff 2 2 make ton and toff big enough to avoid bus contention. ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ? a9.62 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 54 figure 31. udma out transfer start timing diagram figure 32. udma out host terminates transfer addr dmarq dmack diow dior buffer_en data write iordy tack tenv tcyc tcyc ton tdzfs tdvs tdvh tdvs tli1 trfs1 addr dmarq dmack diow dior data write iordy buffer_en tack tss tcyc tli2 tcyc1 tdzfs_mli tcvh toff tli3 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 55 r figure 33. udma out device terminates transfer timing parameters are explained in table 30 . table 30. timing parameters udma out burst ata parameter udma out timing parameter value how to meet specid tack tack tack(min) = (time_ack * t) ? (tskew1 + tskew2) calculate and programming time_ack, see reference manual a9.63 tenv tenv tenv(min) = (time_env * t) ? (tskew1 + tskew2) tenv(max) = (time_env * t) + (tskew1 + tskew2) calculate and programming time_env, see reference manual a9.64 tdvs tdvs tdvs = (time_dvs * t) ? (tskew1 + tskew2) calculate and programming time_dvs, see reference manual a9.65 tdvh tdvh tdvs = (time_dvh * t) ? (tskew1 + tskew2) calculate and programming time_dvh, see reference manual a9.66 tcyc tcyc tcyc = time_cyc * t ? (t skew1 + tskew2) calculate and programming time_cyc, see reference manual a9.67 addr dmarq dmack diow dior data write iordy buffer_en tack tcyc tdzfs_mli tcvh toff tli2 trfs1 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 56 3.3.10 sata phy 1.5 gbps sata phy layer see ?serial ata: high speed serialized at attachment? revision 1.0a, 7-january-2003. 3.3.11 fec ac test timing conditions: ? output loading all outputs: 25 pf t2cyc ? t2cyc = time_cyc * 2 * t calculate and programming time_cyc, see reference manual a9.68 trfs1 trfs trfs = 1.6 * t + tsui + tco + tbuf + tbuf ? a9.69 ? tdzfs tdzfs = time_dzfs * t ? (tskew1) calculate and programming time_dzfs, see reference manual a9.70 tss tss tss = time_ss * t ? (tskew1 + tskew2) calculate and programming time_ss, see reference manual a9.71 tmli tdzfs_mli tdzfs_mli =max(tim e_dzfs, time_mli) * t ? (tskew1 + tskew2) ? a9.72 tli tli1 tli1 > 0 ? a9.73 tli tli2 tli2 > 0 ? a9.74 tli tli3 tli3 > 0 ? a9.75 tcvh tcvh tcvh = (time_cvh *t) ? (tskew1 + tskew2) calculate and programming time_cvh, see reference manual a9.76 ? ton toff ton = time_on * t ? tskew1 toff = time_off * t ? tskew1 ? a9.77 table 31. mii rx signal timing sym description min max unit specid t 1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5 ? ns a11.1 t 2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5 ? ns a11.2 t 3 rx_clk pulse width high 35% 65% rx_clk period 1 a11.3 t 4 rx_clk pulse width low 35% 65% rx_clk period 1 a11.4 table 30. timing parameters udma out burst (continued) ata parameter udma out timing parameter value how to meet specid preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 57 figure 34. ethernet timing diagram ? mii rx signal figure 35. ethernet timing diagra ? mii tx signal figure 36. ethernet timing diagram ? mii async 1 rx_clk shall have a frequency of 25% of data rate of the received signal. see th e ieee 802.3 specification. table 32. mii tx signal timing sym description min max unit specid t 5 tx_clk rising edge to txd[3:0], tx_en, tx_er invalid 3 ? ns a11.5 t 6 tx_clk rising edge to txd[3:0], tx_en, tx_er valid ? 25 ns a11.6 t 7 tx_clk pulse width high 35% 65% tx_clk period 1 1 the tx_clk frequency shall be 25% of the nominal transmit frequency, e.g., a phy operating at 100 mb/s must provide a tx_clk frequency of 25 mhz and a phy operating at 10 mb/s must provide a tx_clk frequency of 2.5 mhz. see the ieee 802.3 specification. a11.7 t 8 tx_clk pulse width low 35% 65% tx_clk period 1 a11.8 table 33. mii async signal timing sym description min max unit specid t 9 crs, col minimum pulse width 1. 5 ? tx_clk period a11.9 t 4 t 3 t 1 t 2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er t 8 t 7 t 5 tx_clk (input) txd[3:0] (outputs) tx_en tx_er t 6 t 9 crs, col preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 58 figure 37. ethernet timing di agram ? mii serial management 3.3.12 usb ulpi this section specifies the usb ulpi timing. for more information refer to utmi+ low pin interface (ulpi) specification, revi sion 1.1, october 20, 2004. table 34. mii serial management channel signal timing sym description min max unit specid t 10 mdc falling edge to mdio output delay 0 25 ns a11.10 t 11 mdio (input) to mdc rising edge setup 10 ? ns a11.11 t 12 mdio (input) to mdc rising edge hold 0 ? ns a11.12 t 13 mdc pulse width high 1 1 mdc is generated by mpc5121e/mpc5123 with a duty cycle of 50% except when mii_speed in the fec mii_speed control register is changed during operation. see the mpc5121e/mpc5123 reference manual. 160 ? ns a11.13 t 14 mdc pulse width low 1 160 ? ns a11.14 t 15 mdc period 2 2 the mdc period must be set to a value of less than or equal to 2.5 mhz (to be compliant with the ieee mii characteristic) by programming the fec mii_speed c ontrol register. see the mp c5121e/mpc5123 reference manual. 400 ? ns a11.15 t 14 t 13 t 12 mdc (output) mdio (input) mdio (output) t 11 t 10 t 15 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 59 figure 38. ulpi timing diagram note output timing is specified at a nominal 50 pf load. 3.3.13 on-chip usb phy the usb phy is an usb2.0 compatible phy integrated on-chip. see chapter 7 in the usb specification rev. 2.0 at www.usb.org. 3.3.14 sdhc figure 39 depicts the timings of the sdhc. table 35. timing specifications ? ulpi sym description min max units specid t ck clock period 15 ? ns a12.1 t sc , t sd setup time (control in, 8-bit data in) ? 6.0 ns a12.2 t hc , t hd hold time (control in, 8-bit data in) 0.0 - ns a12.3 t dc , t dd output delay (control out, 8-bit data out) ? 9.0 ns a12.4 clock t sc t hc t sd t hd t dc t dc t dd control in (dir, nxt) data in (8-bit) control out (stp) data out (8-bit) preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 60 figure 39. sdhc timing diagram table 36 lists the timing parameters. . table 36. mmc/sd interf ace timing parameters id parameter symbols min max unit specid card input clock sd1 clock frequency (low speed) f pp 1 1 in low speed mode, card clock must be lower th an 400 khz, voltage ranges from 2.7 to 3.6 v. 0 400 khz a14.1 clock frequency (sd/sdio full speed/high speed) f pp 2 2 in normal data transfer mode for sd/sdio card, clock frequency can be any value between 0 ~ 25 mhz. 0 25/50 mhz a14.2 clock frequency (mmc full speed/high speed) f pp 3 3 in normal data transfer mode for mmc card, clock frequency can be any value between 0 ~ 20 mhz. 0 20/52 mhz a14.3 clock frequency (identification mode) f od 4 4 in card identification mode, card clock must be 10 0 khz ~ 400 khz, voltage ranges from 2.7 to 3.6 v. 100 400 khz a14.4 sd2 clock low time (full speed/high speed) t wl 10/7 ns a14.5 sd3 clock high time (full speed/high speed) t wh 10/7 ns a14.6 sd4 clock rise time (full speed/high speed) t tlh 10/3 ns a14.7 sd5 clock fall time (full speed/high speed) t thl 10/3 ns a14.8 sdhc output / card inputs cmd, dat (reference to clk) sd6 sdhc output for card input setup t osu 15 ns a14.9 sd7 sdhc output for card input hold t oh 15 ns a14.10 sdhc input / card outputs cmd, dat (reference to clk) sd8 sdhc input setup time t isu 8n s a 1 4 . 1 1 sd1 sd3 sd5 sd7 sd4 sd8 mmcx_cmd output from sdhc to card mmcx_dat_1 mmcx_dat_2 mmcx_dat_3 mmcx_dat_0 mmcx_cmd input from card to sdhc mmcx_dat_1 mmcx_dat_2 mmcx_dat_3 mmcx_dat_0 mmcx_clk sd2 sd6 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 61 3.3.15 diu the diu is a display controller designed to manage the tft lcd display. 3.3.15.1 interface to tft lcd pa nels, functional description figure 40 depicts the lcd interface timing for a ge neric active matrix color tft panel. in this figure signals are shown with positive polarity. th e sequence of events for activ e matrix interface timing is: ? diu_clk latches data into the panel on its positive edge (when positive polarity is selected). in active mode, diu_clk runs continuously. this signal frequency could be from 5 to 100 mhz depending on the panel type. ? diu_hsync causes the panel to start a new line. it always encompasses at least one diu_clk pulse. ? diu_vsync causes the panel to start a new frame. it always encompasses at least one diu_hsync pulse. ? diu_de acts like an output enable signal to the lcd panel. this output enables the data to be shifted onto the display. when disabled, the data is invalid and the trace is off. figure 40. interface timing diagram for tft lcd panels 3.3.15.2 interface to tft lcd pane ls, electrical characteristics figure 41 depicts the horizontal timing (timing of one line), includi ng the horizontal sync pulse and the data. all parameters shown in the diagram are programmable. this timing diagram corresponds to positive polarity of the diu_clk signal (meaning the data and sync. signals change at the rising edge of it) and active- high polarity of the diu_hsync, diu_vsync and diu_de signal. you can select the polarity of the diu_hsync and diu_ vsync signal via the syn_pol register, whether active-high or active-low, the defa ult is active-high. the diu_de signal is always active-high. and, pixel clock inversion and a flexible programmable pixel clock delay is al so supported, programed via the diu clock config register (dccr) in the system clock module. diu_ld[23:0] diu_clk diu_de diu_hsync diu_hsync diu_vsync line 1 line 2 line 3 line 4 line n-1 line n 12 3 m-1 m preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 62 figure 41. tft lcd interface timing diagram ? horizontal sync pulse figure 42 depicts the vertical timing (timing of one frame), including the vertical sync pulse and the data. all parameters shown in the diagram are programmable. figure 42. tft lcd interface timing diagram ? vertical sync pulse table 39 shows timing parameters of signals. table 37. lcd interface timing parameters ? pixel level name description value unit specid t pcp display pixel clock period 15 1 ns a15.1 t pwh hsync pulse width pw_h * t pcp ns a15.2 t bph hsync back porch width bp_h * t pcp ns a15.3 1 2 3 delta_x t pwh t bph t sw t fph diu_clk diu_ld[23:0] diu_hsync diu_de t pcp 1 invalid data invalid data start of line t hsp 1 2 3 delta_y t pwv t bpv t sh t fpv diu_hsync diu_ld[23:0] diu_vsync diu_de t hsp 1 (line data) start of frame invalid data invalid data t vsp preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 63 the delta_x and delta_y parameters are programmed vi a the disp_size register; the pw_h, bp_h, and fp_h parameters are programmed via the hsyn_para register; and the pw_v, bp_v and fp_v parameters are programmed via the vsyn_para register. see appropriate s ection in the reference manual for detail ed descriptions on these parameters. figure 38 depicts the synchronous display interface timing for access level, and table 39 lists the timing parameters. figure 43. lcd interface timing diagram ? access level t fph hsync front porch width fp_h * t pcp ns a15.4 t sw screen width delta_x * t pcp ns a15.5 t hsp hsync (line) period (pw_h + bp_h + delta_x + fp_h) * t pcp ns a15.6 t pwv vsync pulse width pw_v * t hsp ns a15.7 t bpv vsync back porch width bp_v * t hsp ns a15.8 t fpv vsync front porch width fp_v * t hsp ns a15.9 t sh screen height delta_y * t hsp ns a15.10 t vsp vsync (frame) period (pw_v + bp_v + delta_y + fp_h) * t hsp ns a15.11 1 display interface pixel clock period immediate value (in nanosecond). table 38. lcd interface timing parameters ? access level parameter description min typ max unit specid t ckh lcd interface pixel clock high time t pcp * 0.4 t pcp * 0.5 t pcp * 0.6 ns a15.12 t ckl lcd interface pixel clock low time t pcp * 0.4 t pcp * 0.5 t pcp * 0.6 ns a15.13 t dsu lcd interface data setup time 5.0 - - ns a15.14 t dhd lcd interface data hold time 6.0 - - ns a15.15 t csu lcd interface control signal setup time 5.0 - - ns a15.16 t chd lcd interface control signal hold time 6.0 - - ns a15.17 table 37. lcd interface timing parameters ? pixel level (continued) name description value unit specid t ckh t ckl t dhd t dsu t csu diu_hsync diu_vsync diu_de diu_clk diu_ld[23:0] t chd preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 64 3.3.16 spdif the sony/philips digital interface (spdif) timing is totally async hronous, therefore there is no need for relationship with the clock. 3.3.17 can the can functions are availa ble as tx pins at normal io pads and as rx pins at the vbat_rtc domain. there is no filter for the wakeup dominant pulse. any high-to-lo w edge can cause wakeup, if configured. 3.3.18 i 2 c this section specifies the timing parameters of the inter-integrated circuit (i2c) in terface. refere to the i2c-bus specificati on. table 39. i 2 c input timing specifications ? scl and sda sym description min max units specid 1 start condition hold time 2 ? ip-bus cycle 1 1 inter peripheral clock is defined in the mpc5121e/mpc5123 reference manual. a18.1 2 clock low time 8 ? ip-bus cycle 1 a18.2 4 data hold time 0.0 ? ns a18.3 6 clock high time 4 ? ip-bus cycle 1 a18.4 7 data setup time 0.0 ? ns a18.5 8 start condition setup time (for repeated start condition only) 2 ? ip-bus cycle 1 a18.6 9 stop condition setup time 2 ? ip-bus cycle 1 a18.7 table 40. i 2 c output timing specifications ? scl and sda sym description min max units specid 1 1 1 programming ifdr with the maximum frequency result s in the minimum output timings listed. the i 2 c interface is designed to scale the data transition ti me, moving it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed in ifdr. start condition hold time 6 ? ip-bus cycle 2 2 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on exte rnal signal capacitance and pull-up resistor values a18.8 2 1 clock low time 10 ? ip-bus cycle 2 a18.9 3 3 scl/sda rise time ? 7.9 ns a18.10 4 1 data hold time 7 ? ip-bus cycle 2 a18.11 5 1 scl/sda fall time ? 7.9 ns a18.12 6 1 clock high time 10 ? ip-bus cycle 2 a18.13 7 1 data setup time 2 ? ip-bus cycle 2 a18.14 8 1 start condition setup time (for repeated start condition only) 20 ? ip-bus cycle 2 a18.15 9 1 stop condition setup time 10 ? ip-bus cycle 2 a18.16 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 65 note output timing is specified at a nominal 50 pf load. figure 44. timing diagram ? i 2 c input/output 3.3.19 j1850 see the mpc5121e/mpc5123 reference manual. 3.3.20 psc the programmable serial controllers (psc) support di fferent modes of operation (codec, ac97, spi). 3.3.20.1 codec mode (8,16,24 and 32-bit)/i 2 s mode note output timing is specified at a nominal 50 pf load. 3 inter peripheral clock is defined in the mpc5121e/mpc5123 reference manual table 41. timing specifications ? 8,16, 24, and 32-bit codec/i 2 s master mode sym description min typ max units specid 1 bit clock cycle time, programmed in ccs register 40.0 ? ? ns a20.1 2 clock duty cycle 45 50 55 % 1 1 bit clock cycle time a20.2 3 bit clock fall time ? ? 7.9 ns a20.3 4 bit clock rise time ? ? 7.9 ns a20.4 5 framesync valid after clock edge ? ? 8.4 ns a20.5 6 framesync invalid after clock edge ? ? 8.4 ns a20.6 7 output data valid after clock edge ? ? 9.3 ns a20.7 8 input data setup time 6.0 ? ? ns a20.8 1 2 3 4 5 6 7 8 9 scl sda preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 66 figure 45. timing diagram ? 8,16, 24, and 32-bit codec/i 2 s master mode note output timing is specified at a nominal 50 pf load. table 42. timing specifications ? 8,16, 24, and 32-bit codec/i 2 s slave mode sym description min typ max units specid 1 bit clock cycle time 40.0 ? ? ns a20.9 2 clock duty cycle ? 50 ? % 1 1 bit clock cycle time a20.10 3 framesync setup time 1.0 ? ? ns a20.11 4 output data valid after clock edge ? ? 14.0 ns a20.12 5 input data setup time 1.0 ? ? ns a20.13 6 input data hold time 1.0 ? ? ns a20.14 bitclk 5 3 4 3 4 (clkpol=0) bitclk (clkpol=1) framesync (syncpol = 1) txd output output output 6 7 8 output framesync (syncpol = 0) output rxd input 1 22 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 67 figure 46. timing diagram ? 8, 16, 24, and 32-bit codec/i 2 s slave mode 3.3.20.2 ac97 mode note output timing is specified at a nominal 50 pf load. table 43. timing specifications ? ac97 mode sym description min typ max units specid 1 bit clock cycle time ? 81.4 ? ns a20.15 2 clock pulse high time ? 40.7 ? ns a20.16 3 clock pulse low time ? 40.7 ? ns a20.17 4 framesync valid after rising clock edge ? ? 13.0 ns a20.18 5 output data valid after rising clock edge ? ? 14.0 ns a20.19 6 input data setup time 1.0 ? ? ns a20.20 7 input data hold time 1.0 ? ? ns a20.21 bitclk 3 (clkpol=0) bitclk (clkpol=1) framesync (syncpol = 1) txd output input input 4 5 input framesync (syncpol = 0) input rxd input 1 22 6 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 68 figure 47. timing diagram ? ac97 mode 3.3.20.3 spi mode note output timing is specified at a nominal 50 pf load. table 44. timing specifications ? spi master mode, format 0 (cpha = 0) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a20.26 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a20.27 3 slave select clock delay, programable in the psc ccs register 30.0 ? ns a20.28 4 output data valid after slave select (ss ) ? 8.9 ns a20.29 5 output data valid after sck ? 8.9 ns a20.30 6 input data setup time 6.0 ? ns a20.31 7 input data hold time 1.0 ? ns a20.32 8 slave disable lag time ? tsck ns a20.33 9 sequential transfer delay, programable in the psc ctur / ctlr register 15.0 ? ns a20.34 10 clock falling time ? 7.9 ns a20.35 11 clock rising time ? 7.9 ns a20.36 bitclk (clkpol=0) framesync (syncpol = 1) sdata_out output input 6 output sdata_in input 1 4 3 5 2 7 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 69 figure 48. timing diagram ? spi master mode, format 0 (cpha = 0) note output timing is specified at a nominal 50 pf load. table 45. timing specifications ? spi slave mode, format 0 (cpha = 0) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a20.37 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a20.38 3 slave select clock delay 1.0 ? ns a20.39 4 input data setup time 1.0 ? ns a20.40 5 input data hold time 1.0 ? ns a20.41 6 output data valid after ss ? 14.0 ns a20.42 7 output data valid after sck ? 14.0 ns a20.43 8 slave disable lag time 0.0 ? ns a20.44 9 minimum sequential transfer delay = 2 * ip bus clock cycle time 30.0 ? ? a20.45 sck (clkpol=0) sck (clkpol=1) mosi output output output ss output miso input 1 22 8 9 3 4 5 6 6 7 7 11 10 10 11 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 70 figure 49. timing diagram ? spi slave mode, format 0 (cpha = 0) note output timing is specified at a nominal 50 pf load. table 46. timing specifications ? spi master mode, format 1 (cpha = 1) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a20.46 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a20.47 3 slave select clock delay, programable in the psc ccs register 30.0 ? ns a20.48 4 output data valid ? 8.9 ns a20.49 5 input data setup time 6.0 ? ns a20.50 6 input data hold time 1.0 ? ns a20.51 7 slave disable lag time ? tsck ns a20.52 8 sequential transfer delay, programable in the psc ctur / ctlr register 15.0 ? ns a20.53 9 clock falling time ? 7.9 ns a20.54 10 clock rising time ? 7.9 ns a20.55 sck (clkpol=0) sck (clkpol=1) mosi input input input ss input miso output 1 22 9 3 7 4 6 5 8 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 71 figure 50. timing diagram ? spi master mode, format 1 (cpha = 1) note output timing is specified at a nominal 50 pf load. table 47. timing specifications ? spi slave mode, format 1 (cpha = 1) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a20.56 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a20.57 3 slave select clock delay 0.0 ? ns a20.58 4 output data valid ? 14.0 ns a20.59 5 input data setup time 2.0 ? ns a20.60 6 input data hold time 1.0 ? ns a20.61 7 slave disable lag time 0.0 ? ns a20.62 8 minimum sequential transfer delay = 2 * ip-bus clock cycle time 30.0 ? ns a20.63 sck (clkpol=0) sck (clkpol=1) mosi output output output ss output miso input 1 22 7 8 3 4 6 10 9 9 10 5 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 72 figure 51. timing diagram ? spi slave mode, format 1 (cpha = 1) 3.3.21 gpios and timers the mpc5121e/mpc5123 contains several sets of i/os that do not require special setup, hold, or valid requirements. the external events (gpio or timer inputs) are asynchronous to the sy stem clock. the inputs must be valid for at least tiowid to ensure proper capture by the internal ip clock. 3.3.22 fusebox table 49 gives the fusebox specification. table 48. gpio/timers input ac timing specifications symbol description min unit specid t iowid gpio/timers inputs - minimum pulse witdh 2t 1 1 t is the ip bus clock cycle. t= 12 ns is the minimu m value (for the maximum ip bus freqency of 83 mhz). ns a21.1 table 49. fusebox characteristics sym description min max units specid t fusewr program time 1 for fuse 1 the program length is defined by the value defined in the epm_pgm_length bits of the iim module. 125 ? us a22.1 i fusewr program current to program one fuse bit ? 10 ma a22.2 sck (clkpol=0) sck (clkpol=1) mosi input input input ss input miso output 1 22 7 8 3 4 6 5 preliminary
electrical and thermal characteristics mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 73 3.3.23 ieee 1149.1 (jtag) figure 52. timing diagram ? jtag clock input table 50. jtag timing specification sym characteristic min max unit specid ? tck frequency of operation 0 25 mhz a23.1 1 tck cycle time 40 ? ns a23.2 2 tck clock pulse width measured at 1.5v 1 . 08 ? ns a23.3 3 tck rise and fall times 0 3 ns a23.4 4trst setup time to tck falling edge 1 1 trst is an asynchronous signal. the setup time is for test purposes only. 10 ? ns a23.5 5trst assert time 5 ? ns a23.6 6 input data setup time 2 2 non-test, other than tdi and tms, signal input timing with respect to tck. 5 ? ns a23.7 7 input data hold time 2 15 ? ns a23.8 8 tck to output data valid 3 3 non-test, other than tdo, signal ou tput timing with respect to tck. 030nsa23.9 9 tck to output high impedance 3 0 30 ns a23.10 10 tms, tdi data setup time. 5 ? ns a23.11 11 tms, tdi data hold time. 1 ? ns a23.12 12 tck to tdo data valid. 0 15 ns a23.13 13 tck to tdo high impedance. 0 15 ns a23.14 tck vm vm vm 3 3 22 1 vm = midpoint voltage numbers shown reference jtag timing specification table preliminary
mpc5121e/mpc5123 data sheet, rev. 1 electrical and thermal characteristics freescale semiconductor 74 figure 53. timing diagram ? jtag trst figure 54. timing diagram ? jtag boundary scan figure 55. timing diagram ? test access port tck trst 5 4 numbers shown reference jtag timing specification table tck input data valid output data valid data inputs data outputs data outputs 6 7 8 9 numbers shown reference jtag timing specification table tck input data valid output data valid tdi, tms tdo tdo 10 11 12 13 numbers shown reference jtag timing specification table preliminary
system design information mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 75 3.3.24 viu the video input unit (viu) is an interface which accepts the itu656 format co mpatible video stream. figure 56 shows the viu interface timing and table 51 lists the timing parameters. figure 56. viu interface timing diagram 4 system design information 4.1 power up/down sequencing power sequencing between the 1.4 v power supply vdd_core a nd the remaing supplies is required to prevent excessive current during power up phase. the recommended power sequence is as follows: ? use 12v/millisecond or slower time for all supplies. ? power up vdd_io, pll_avdd, vbat_rtc (if not appl ied permanently), vdd_mem _io, avdd_fuserd, usb phy & sata phy supplies first in any order and then power up vdd_core. if required avdd_fusewr should be powered up afterwards. ? all the supplies must reach the specified operating conditions before the poreset can be released. ? for power down, drop avdd_fusewr to 0v first, drop vdd_core to 0v, and then drop all other supplies. ? vdd_core should not exceed vdd_io, vdd_mem_io, vbat_rtc or pll_avdds by more than 0.4 v at any time, including power-up. 4.2 system and cpu core avdd power supply filtering each of the independent pll power supplies require filtering external to the device. the following drawing figure 57 is a recommendation for the required filter circuit. each circuit should be placed as close as possible to the specific av dd pin being supplied to minimize noise coupled from nearby circuits. all traces should be as low impeda nce as possible, especially gr ound pins to th e ground plane. table 51. viu interface timing parameters parameter description min typ max unit specid f pix_ck viu pixel clock frequency - - 83 mhz a24.1 t dsu viu data setup time 2.5 - - ns a24.2 t dhd viu data hold time 2.5 - - ns a24.3 f pix_clk t dhd t dsu viu_pix_clk viu_data[9:0] preliminary
mpc5121e/mpc5123 data sheet, rev. 1 system design information freescale semiconductor 76 the filter for system/core pllvdd to vss should be connected to the power and ground planes, respectively, not fingers of the planes. in addition to keeping the filter components for system/core pl lvdd as close as practical to the body of the mpc5121e as previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise onto the portion of that supply between the filter and the mpc5121e. the capacitors for c2 in the figure below should be rated x5r or better due to temperature performance. figure 57. power supply filtering 4.3 connection recommendations to ensure reliable operation, connect unused inputs to an approp riate signal level. unused active low inputs should be tied to vdd_io. unused active high inputs should be connected to vs s. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd and vss pins of the mpc5121e/mpc5123. the unused avdd_fusewr power should be co nnecetd to vss directly or via a resistor. for ddr or lpddr modes the unused pins vtt[3:0] for ddr2 termination voltage can be unconnected. the sata phy needs to be powered even if it is not used in an application. in this case, you should not enable the sata oscillator and the sa ta phy by software. figure 58. recommended connection for pins of unused sata phy avdd device pin power supply source r1=10 c1=1 f c2=0.1 f sata_xtalo s ata _ x ta l i vss nc sata_resref sata_anaviz nc nc sata_txn sata_txp nc nc sata_rxn sata_rxp nc nc sata_vdda_1p2 sata_vdda_3p3 vdd_core sata_pll_vdda1p2 sata_vdda_vreg 1.7-2.6v sata_rx_vssa sata_pll_vssa vss vss sata_tx_vssa vss vdd_core vdd_io mpc5121e/mpc5123 preliminary
system design information mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 77 figure 59. recommended connection for pins of unused usb phy 4.4 pull-up/pull-down resistor requirements the mpc5121e/mpc5123 requires external pull-up or pull-down resistors on certain pins. 4.4.1 pull-down resistor re quirements for test pin the mpc5121e/mpc5123 requires a pull-down resistor on the test pin test. 4.4.2 pull-up requirements for the pci control lines pci control signals always require pull-up resistors on the moth erboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. this includes pci_frame , pci_trdy , pci_irdy , pci_devsel , pci_stop , pci_serr , pci_perr , and pci_req . refer to the pci local bus specification. 4.5 jtag the mpc5121e/mpc5123 provides you with an ieee 1149.1 jtag inte rface to facilitate board/system testing. it also provides a common on-chip processor (cop) interface, which shares the ieee 1149.1 jtag port. the cop interface provides access to the mpc5121e/mpc5123's embedded e300 processor and to other on-chip resources. this interface provides a means for executing test routines a nd for performing software deve lopment and debug functions. 4.5.1 trst boundary scan testing is enabled th rough the jtag interface signals. the t rst signal is optional in the ieee 1149.1 specification but is provided on all processors that implement the powerpc architecture. to obtain a reliable power-on reset performance, the t rst signal must be asserted during power-on reset. usb_xtalo usb_xtali vss nc usb_tpa nc usb_dn usb_dp weak pull-up or pull-down usb_uid usb_vbus vss usb_pll_pwr3 usb_pll_gnd vss usb_vssa_bias usb_rref vss vss usb_vdda_bias vss vss vdd_io usb_vssa vss usb_vdda vdd_io mpc5121e/mpc5123 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 system design information freescale semiconductor 78 4.5.1.1 trst and poreset the jtag interface can control the directi on of the mpc5121e/m pc5123 i/o pads vi a the boundary scan chain. the jtag module must be reset before the mpc5121e/mpc5123 come s out of power-on reset; do this by asserting trst before poreset is released. for more details refer to the reset and jtag timing specification. figure 60. poreset vs. trst 4.5.2 e300 cop/bdm interface there are two possibilities to connect the jtag interface: us ing it with a cop connector and without a cop connector. 4.5.2.1 boards interfacing the jtag port via a cop connector the mpc5121e/mpc5123 functional pin interface and internal logic provides access to the embedded e300 processor core through the freescale standard cop/bdm interface. table 52 gives the cop/bdm interface signals. the pin order shown reflects only the cop/bdm connector order. table 52. cop/bdm interface signals bdm pin # mpc5121e/mpc51 23 i/o pin bdm connector internal pull up/down external pull up/down i/o 1 16 ? gnd ? ? ? 15 ckstp_out ckstp_out ? 10k pull-up i 14 ? key ? ? ? 13 hreset hreset pull-up 10k pull-up o 12 ? gnd ? ? ? 11 sreset sreset pull-up 10k pull-up o 10 ? n/c ? ? ? 9 tms tms pull-up 10k pull-up o 8 ckstp_in ckstp_in ? 10k pull-up o 7 tck tck pull-up 10k pull-up o 6? v d d 2 ??? 5see note 3 halted 3 ??i 4trst trst pull-up 10k pull-up o 3 tdi tdi pull-up 10k pull-up o trst poreset required assertion of trst optional assertion of trst preliminary
system design information mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 79 for a board with a cop (common on-chip proces sor) connector that accesses the jtag inte rface and needs to reset the jtag module, only wiring trst and poreset is not recommended. to reset the mpc5121e/mpc5123 via the cop connector, the hreset pin of the cop should be connected to the hreset pin of the mpc5121e/mpc5123. the circuitry shown in figure 61 allows the cop to assert hreset or trst separately, while any other board sources can drive poreset . 2see note 4 qack 4 ??o 1tdo tdo ? ? i 1 with respect to the emulator tool?s perspective: input is really an output from the embedded e300 core. output is really an input to the core. 2 from the board under test, power sense for chip power. 3 halted is not available from e300 core. 4 input to the e300 core to enable/disable soft-stop condition during breakpoints. mpc5121e/mpc5123 internally ties core_qack to gnd in its normal/functional mode (always asserted). table 52. cop/bdm interface signals (continued) bdm pin # mpc5121e/mpc51 23 i/o pin bdm connector internal pull up/down external pull up/down i/o 1 preliminary
mpc5121e/mpc5123 data sheet, rev. 1 system design information freescale semiconductor 80 figure 61. cop connector diagram 4.5.2.2 boards without cop connector if the jtag interface is not used, trst should be tied to poreset , so that it is asserted when the system reset signal (poreset ) is asserted. this ensures that the jtag scan chain is initialized during power on. figure 62 shows the connection of the jtag interface without cop connector. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 k 16 14 hreset sreset vdd_io vdd_io trst vdd_io tms vdd_io tck vdd_io tdi ckstp_out tdo 3 11 16 4 9 12 7 6 2 15 1 10 5 (3) 2 (4) 13 nc nc nc tdo hreset sreset trst tms tck tdi ckstp_out vdd_io 10kohm 10kohm 10kohm 10kohm 10kohm cop header cop connector physical pinout halted qack vdd_io 10kohm poreset poreset vdd_io 10kohm ckstp_in (lpc_clk) 8 ckstp_in vdd_io 10kohm preliminary
package information mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 81 figure 62. trst wiring for boards without cop connector 5 package information this section details package parameters and dimensions. th e mpc5121e/mpc5123 is available in a thermally enhanced plastic ball grid array (tepbga), see section 5.1, ?package parameters ,? and section 5.2, ?mechanical dimensions ,? for information on the tepbga. hreset sreset vdd_io vdd_io trst vdd_io jtag_tms vdd_io tck vdd_io tdi ckstp_out tdo hreset sreset 10 kohm 10 kohm poreset poreset 10 kohm 10 kohm 10 kohm preliminary
mpc5121e/mpc5123 data sheet, rev. 1 package information freescale semiconductor 82 5.1 package parameters 5.2 mechanical dimensions table 53. tepbga paramaters package outline 27 mm 27 mm interconnects 516 pitch 1.00 mm module height (typical) 2.25 mm solder balls 96. 5 sn/3.5ag (vy package) ball diameter (typical) 0.6 mm preliminary
package information mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 83 figure 63. ball map for the mpc5121e 516-pbga package 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 a vss vss sata_ rxn sata_ rxp sata_ rx_v ssa psc7_ 4 psc7_ 3 psc6_ 4 psc6_ 2 psc6_ 0 psc11 _0 psc10 _2 psc2_ 3 psc1_ 3 psc1_ 1 psc0_ 1 can1 _tx gpio2 8 xtalo _rtc usb2_ drvv bus usb_ dm usb_ dp usb_ tpa vss b vss vss vss sata_ rx_v ssa vss psc8_ 3 vss psc7_ 0 psc6_ 3 vdd_i o psc11 _1 vss psc10 _1 psc2_ 1 vdd_i o psc0_ 4 vss gpio3 1 can2 _rx vss usb2_ vbus _pwr _faul t vss usb_ vssa _bias usb_ xtalo vdd_i o vss c vss sata_ xtalo sata_ xtali vss sata_ vd da _1p2 psc9_ 0 psc8_ 2 psc7_ 2 avdd _fus ewr psc6_ 1 psc11 _2 psc10 _3 psc10 _0 psc2_ 0 psc1_ 0 psc0_ 3 psc_ mclk _in gpio3 0 can1 _rx xtali _rtc usb_ vdda usb_ vssa vss usb_ xtali vss pci_c lk d sata_ vdda _1p2 vss sata_ pll_v ssa sata_ vdda _3p3 sata_ vdda _vre g psc9_ 3 psc9_ 1 psc8_ 1 avdd _fus erd vdd_i o psc11 _4 vss psc2_ 4 psc1_ 4 vdd_i o psc0_ 0 vss hib_m ode vbat_ rtc usb_ vdda usb_ vbus usb_ vdda _bias usb_ pll_p wr3 vss vss pci_r eq2 e sata_ txn sata_ vdda _1p2 sata_ pll_v dda1 p2 sata_ resr ef sata_ anavi z psc9_ 4 psc9_ 2 psc8_ 4 psc8_ 0 psc7_ 1 psc11 _3 psc10 _4 psc2_ 2 psc1_ 2 psc0_ 2 can2 _tx gpio2 9 vss usb_ uid usb_ vssa usb_ vssa usb_ rref usb_ pll_g nd pci_g nt2 pci_g nt0 pci_r eq1 f sata_ txp vss vss vss vss vss vss vss vdd_i o vdd_i o vdd_i o vss vss vdd_i o vss pci_r st vdd_i o pci_a d30 vdd_i o pci_a d28 g sata_ tx_vs sa nfc_ re nfc_ we nfc_ wp vss pci_g nt1 pci_r eq0 pci_a d29 pci_a d26 pci_c be3 h nfc_ rb pata _ dack nfc_ ce0 nfc_ ale nfc_ cle vss vdd_i o pci_a d31 vss pci_a d24 vss pci_a d21 j pata _ i or pata _ i ochr dy pata _ i ntrq pata _ drq vdd_i o pci_a d27 pci_a d25 pci_a d23 pci_a d20 pci_a d18 k pata _ ce1 vdd_i o pata _ i solat e vdd_i o pata _ i ow vss vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vss pci_i dsel pci_a d22 pci_a d19 pci_a d17 pci_i rdy l emb_ ad03 emb_ ad02 emb_ ad01 emb_ ad00 pata _ ce2 vss vdd_ core vss vss vss vss vss vss vdd_ core vss pci_a d16 vdd_i o pci_c be2 vdd_i o pci_d evse l m emb_ ad06 vss emb_ ad05 vss emb_ ad04 vdd_ core vss vss vss vss vss vss vdd_ core pci_t rdy pci_f rame pci_s top pci_p err pci_s err n emb_ ad10 emb_ ad09 emb_ ad08 emb_ ad07 vss vdd_i o vdd_ core vss vss vss vss vss vss vdd_ core vdd_i o pci_p ar vss pci_c be1 vss pci_a d15 p emb_ ad15 emb_ ad14 emb_ ad11 emb_ ad13 emb_ ad12 vdd_i o vdd_ core vss vss vss vss vss vss vdd_ core vdd_i o pci_c be0 pci_a d09 pci_a d13 pci_a d14 pci_a d12 r emb_ ad17 vdd_i o emb_ ad16 vdd_i o emb_ ad19 vdd_ core vss vss vss vss vss vss vdd_ core pci_a d03 pci_a d06 pci_a d10 pci_a d11 pci_a d08 t emb_ ad22 emb_ ad18 emb_ ad20 emb_ ad21 emb_ ad23 vss vdd_ core vss vss vss vss vss vss vdd_ core vss sys_ pll _a vdd vdd_i o pci_a d05 vdd_i o pci_a d07 u emb_ ad25 vss emb_ ad24 vss emb_ ad29 vss vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vdd_ core vss sys_ pll_a vss pci_i nta pci_a d00 pci_a d02 pci_a d04 v emb_ ad26 emb_ ad27 emb_ ad28 emb_ ad30 emb_ ax01 sres et vss sys_ xtali vss pci_a d01 w emb_ ad31 emb_ ax00 emb_ ax02 lpc_a x03 lpc_ cs0 vdd_i o vdd_i o tdo pore set hres et test sys_ xtalo y lpc_ cs2 vdd_i o lpc_ cs1 vdd_i o lpc_ oe j1850 _tx tdi vss tms ckst p_ou t aa lpc_ rwb lpc_a ck psc4_ 1 lpc_ clk psc4_ 3 vss vdd_ mem_i o vss vss vdd_ mem_i o vdd_ mem_i o vss vss core _pll_ avdd vss i2c2_ sda vdd_i o j1850 _rx vdd_i o trst ab psc4_ 0 vss psc4_ 2 vss psc3_ 1 mdq1 mvtt 0 mdq5 mdq1 0 vss mvre f mdq1 9 mdq2 1 mdq2 7 mdq3 1 ma1 ma5 vdd_ mem_i o ma14 mcke spdif _txcl k i2c1_ scl i2c1_ sda vss irq1 tck ac psc5_ 0 psc4_ 4 psc5_ 1 psc3_ 2 vdd_ mem_i o mdm0 mdq8 vss mdq1 4 vdd_ mem_i o mdqs 2 vss mdq2 5 vdd_ mem_i o mdq3 0 mba1 vss ma7 ma11 vdd_ mem_i o modt vss i2c0_ scl spdif _rx i2c2_ scl irq0 ad psc5_ 2 psc5_ 3 vss psc3_ 3 mdqs 0 mdq6 mdq1 1 mdqs 1 vdd_ mem_i o mdq1 6 mdq1 8 mdq2 0 mdq 2 3 mdqs 3 mdq2 9 mba0 ma0 ma4 ma9 ma13 mwe mcs core _pll_ avss spdif _tx vss i2c0_ sda ae vdd_i o vdd_i o psc5_ 4 mdq2 vdd_ mem_i o mdq7 vss mdm1 mdq1 2 vdd_ mem_i o mvtt 2 vss mdq2 4 mvtt 3 vdd_ mem_i o mdq2 8 vss ma2 ma6 vdd_ mem_i o ma12 ma15 vss vdd_i o vdd_i o vss af vdd_i o psc3_ 0 psc3_ 4 mdq0 mdq3 mdq4 mdq9 mvtt 1 mdq1 3 mdq1 5 mdq1 7 mdm2 mdq2 2 mdq2 6 mdm3 mck mck mba2 ma3 ma8 ma10 mras mcas vdd_i o preliminary
mpc5121e/mpc5123 data sheet, rev. 1 package information freescale semiconductor 84 figure 64 shows the mechanical dimensions and bottom surf ace nomenclature of the mpc5121e/mpc5123 516-pbga package. figure 64. mechanical dimension and bottom surface nomenclature of the mpc5121e/mpc5123 tepbga 1 all dimensions are in millimeters. 2 dimensions and tolerances per asme y14.5m-1994. 3 maximum solder ball diameter measured parallel to datum a. 4 datum a, the seating plane, is determined by the spherical crowns of the solder balls. preliminary
product documentation mpc5121e/mpc5123 data sheet, rev. 1 freescale semiconductor 85 6 product documentation this data sheet is labeled as a particular type: product previe w, advance information, or tech nical data. definitions of these types are available at: http://www.freescale.com. table 54 provides a revision history for this document. table 54. document revision history revision substantive change(s) rev. 0, drafta first draft (5/2008) rev. 0, draftb second draft (5/2008) rev. 0, draftc third draft (7/2008) preliminary
document number: mpc5121e rev. 1 10/2008 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved. this page intentionally blank preliminary

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